 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| amd preliminary information AMD-8111 hypertransport i/o hub data sheet the amd athlon 64 and amd opteron processors power the next generation in computing platforms, designed to deliver the ultimate performance for cutting-edge applications and an unprecedented computing experience. the amd-8000 series of chipset components is a highly integrated system logic solution that delivers enhanced performance and features for the amd athlon 64 and amd opteron processors. the AMD-8111 hypertransport i/o hub includes the following features: hypertransport technology link supports up to 800 megabytes per second of total bandwidth, using 8-bit hypertransport input and output links running simultaneously with a 200 mhz (double pumped) clock supports multiple bit widths, including eight bits, four bits, and two bits (input and output) supports a 200-mhz(double pumped) hypertransport clock pci bus utilizes a 33-mhz, 32-bit interface pci version 2.2 compliant includes pci bus arbiter with support for up to eight external devices ac ?7 support ac ?7 version 2.2 compatible soft modem and 6-channel soft audio interface advanced communication riser (acr) rev. 1.0 support ethernet lan controller 10/100-mbit/s uses mii interface to connect to the ethernet phy system management bus one system management bus 1.0 host controller one system management bus 2.0 host controller usb support for six ports usb 1.1 support provided by two ohci-based usb hosts, each supporting three ports usb 2.0 support provided by one ehci-based host, which supports all six ports enhanced ide controller support for a primary and a secondary dual-drive port pio modes 0?, multi-word dma modes 0?, udma modes 0? (through to ata-133), and atapi two independent controllers for dma accesses lpc bus connects peripherals such as super i/o and bios high precision event timer supports one 32-bit counter with one periodic and two non-periodic timers serial irq protocol extensive acpi-compliant power management programmable c2, c3, power-on-suspend, suspend to ram, suspend to disk, and soft off states throttling device monitors hardware traps system inactivity timers thirty-two general purpose i/o (gpio) pins many are multiplexed with other hard-wired functions privacy/security logic; rom access control 24674 publication # 3.00 revision: april 2003 issue date:
amd preliminary information 24674 rev. 3.00 april 2003 AMD-8111 hypertransport i/o hub data sheet legacy at-compatible logic programmable interrupt controller programmable interval timer dma controller (lpc bus) legacy ports ioapic controller real-time clock includes 256 bytes of cmos, battery-powered ram, and acpi-compliant extensions battery-powered ram 256 bytes for storing cpu memory controller context random number generator 492-pin bga; 26-by-26 bga grid; 35-by-35 millimeters square 1.8-v core; 3.3-v output drivers; 5-v tolerant input buffers figure 1. system block diagram pci bus usb 1394a 32-bit eide AMD-8111 hypertransport i/o hub hypertransport link 8/8 lpc super i/o bios ac ?7 ethernet smbus host tunnel 3 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information trademarks amd, the amd arrow logo, and combinations thereof, amd athlon, amd opteron amd-8000, AMD-8111, magic packet, and pcnet are trademarks of advanced micro devices, inc. hypertransport is a licensed trademark of the hypertransport technology consortium. microsoft is a registered trademark of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies. disclaimer the contents of this document are provided in connection with advanced micro devices, inc. ( amd? products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including , but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual prop erty right. amd s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical impla nt into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the r ight to discontinue or make changes to its products at any time without notice. ?2001 - 2003 advanced micro devices, inc. all rights reserved. 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information table of contents 5 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information table of contents chapter 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 chapter 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.1 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.2 host hypertransport technology interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.3 secondary pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.4 lpc bus and legacy support pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.5 ultra dma enhanced ide interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.6 system management pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.7 universal serial bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.8 ac ?7 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.9 mii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.10 test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.11 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.12 power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 chapter 3 functional operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.1.1 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.2 error reporting and handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.1.3 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 9 3.2 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.2.1 hypertransport technology host interface . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.3 secondary pci bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.4 lpc bridge and legacy logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.4.1 legacy and miscellaneous support logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.4.2 interrupt controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.4.3 watchdog timer (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.4.4 high precision event timer (hpet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.4.5 real-time clock (logic powered by vdd_coreal) . . . . . . . . . . . . . . . . . . .50 6 table of contents AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.5 enhanced ide controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.6 system management bus 2.0 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.6.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.6.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 0 3.7 system management logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.7.1 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.7.2 serial irq protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 3.7.3 smbus 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 3.7.4 plug and play irqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 3.7.5 general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 3.8 ac '97 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 3.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 3.8.2 ac ?7 serial link interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 3.8.3 ac '97 pci interface and bus master controller . . . . . . . . . . . . . . . . . . . . . . . . .70 3.8.4 ac '97 data buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 3.8.5 ac '97 power management logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 3.8.6 ac ?7 link reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 3.9 usb controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 3.9.1 usb interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 3.10 lan ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 3.10.1 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.10.2 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 3.10.3 software interrupt timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 3.10.4 media access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 3.10.5 transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 3.10.6 receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 3.10.7 statistics counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 3.10.8 vlan support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 3.10.9 loopback operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 3.10.10 full-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 3.10.11 external phy interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 table of contents 7 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 3.10.12 network port manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 3.10.13 auto-negotiation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 3.10.14 regulating network traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 3.10.15 delayed interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 3.10.16 power management support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 3.10.17 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 chapter 4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 4.1 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5 4.1.1 configuration space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 4.1.2 register naming and description conventions . . . . . . . . . . . . . . . . . . . . . . . . .136 4.1.3 positively- and subtractively-decoded spaces . . . . . . . . . . . . . . . . . . . . . . . . .138 4.2 pci bridge configuration registers (deva:0xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . .139 4.3 lpc bridge configuration registers (devb:0xxx) . . . . . . . . . . . . . . . . . . . . . . . . . .149 4.4 legacy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 64 4.4.1 miscellaneous fixed i/o space registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 4.4.2 legacy dma controller (dmac) registers . . . . . . . . . . . . . . . . . . . . . . . . . . .167 4.4.3 legacy programmable interval timer (pit) registers . . . . . . . . . . . . . . . . . . .169 4.4.4 legacy programmable interrupt controller (pic) . . . . . . . . . . . . . . . . . . . . . . .170 4.4.5 ioapic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 4.4.6 watchdog timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 4.4.7 high precision event timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 4.4.8 real-time clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 4.5 enhanced ide controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 4.5.1 enhanced ide configuration registers (devb:1xxx) . . . . . . . . . . . . . . . . . . .184 4.5.2 eide bus master i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 4.6 system management bus 2.0 controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 4.6.1 system management bus configuration registers (devb:2xxx) . . . . . . . . . .195 4.6.2 smbus controller interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 4.6.3 host controller interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 4.7 system management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 4.7.1 system management configuration registers (devb:3xxx) . . . . . . . . . . . . . .203 8 table of contents AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 4.7.2 system management i/o mapped registers (pmxx) . . . . . . . . . . . . . . . . . . . . .220 4.8 ac ?7 controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 4.8.1 ac ?7 audio register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 4.8.2 ac '97 modem registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 4.9 usb controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 4.9.1 usb open host controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 4.9.2 usb enhanced host controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 4.10 lan ethernet controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 4.10.1 lan ethernet controller user accessible registers . . . . . . . . . . . . . . . . . . . . .306 4.10.2 lan ethernet controller configuration registers (dev1:0xxx) . . . . . . . . . . .308 4.10.3 memory-mapped registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 4.10.4 receive descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346 4.10.5 transmit descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 chapter 5 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 5.1 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 53 5.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4 5.3 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 5.4 signal groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 5.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6 5.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 8 chapter 6 pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361 chapter 7 package specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 chapter 8 test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 8.1 pin select options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 71 8.1.1 nand tree mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 8.1.2 high impedance mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 appendix a glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375 appendix b references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376 appendix c conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 list of figures 9 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information list of figures figure 1. system block diagram .................................................................................................. ...2 figure 2. interrupt sources..................................................................................................... ........41 figure 3. vectored interrupt routing ............................................................................................ .42 figure 4. high precision event timer block diagram ..................................................................47 figure 5. high precision event timer interrupt routing...............................................................49 figure 6. smbus controller interrupt model.................................................................................52 figure 7. sts to interrupt routing.............................................................................................. ...55 figure 8. device monitors and retrigger timers ..........................................................................56 figure 9. system power state transitions .....................................................................................59 figure 10. transitions from moff to soff and from soff/std/str to fon...........................61 figure 11. transitions from fon to soff/std/str .....................................................................62 figure 12. gpio pin format ...................................................................................................... ......67 figure 13. ac ?7 codec connections ............................................................................................6 8 figure 14. output frame with audio samples in half rate transfer mode ...................................74 figure 15. input frame with audio samples in half rate transfer mode......................................74 figure 16. usb controller building blocks ....................................................................................76 figure 17. receive and transmit descriptor rings .........................................................................81 figure 18. iso 8802-3 (ieee/ansi 802.3) data frame .................................................................90 figure 19. conduit mode transmission with one collision ...........................................................93 figure 20. conduit mode excessive collisions error......................................................................93 figure 21. address match logic.................................................................................................. ....96 figure 22. ieee 802.3 frame and length field transmission order .............................................97 figure 23. vlan-tagged frame format ......................................................................................105 figure 24. internal and external loopback paths ..........................................................................107 figure 25. media independent interface ........................................................................................10 9 figure 26. frame format at the mii interface connection ............................................................111 figure 27. auto-poll and auto-poll data registers.......................................................................113 figure 28. indirect access to auto-poll data registers ................................................................114 figure 29. pattern match ram.................................................................................................... ..129 figure 30. configuration space (primary and secondary bus) .....................................................136 figure 31. ferr_l and ignne_l logic .....................................................................................166 figure 32. receive descriptor format ...........................................................................................3 47 figure 33. format of flags in receive descriptor, offset 08h ..................................................347 figure 34. transmit descriptor format..........................................................................................3 49 figure 35. format of tflags1 in transmit descriptor, offset 00h ............................................350 figure 36. bga designations (top side view) ............................................................................361 10 list of figures AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information list of tables 11 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information list of tables table 1. i/o cell types ......................................................................................................... ........19 table 2. host hypertransport technology pin descriptions ...................................................20 table 3. secondary pci interface pin descriptions......................................................................21 table 4. lpc bus and legacy support pin descriptions .............................................................22 table 5. ultra dma enhanced ide pin descriptions ..................................................................23 table 6. system management pin descriptions............................................................................24 table 7. usb pin descriptions ................................................................................................... ..29 table 8. ac ?7 pin descriptions ................................................................................................ .30 table 9. mii interface pin descriptions........................................................................................3 1 table 10. test pin descriptions ................................................................................................. .....33 table 11. miscellaneous pin descriptions ......................................................................................34 table 12. error handling ........................................................................................................ ........37 table 13. ic clock pins ......................................................................................................... .........39 table 14. hypertransport protocol unit ids..............................................................................40 table 15. interrupt routing configuration .....................................................................................41 table 16. ioapic redirection register connections ....................................................................45 table 17. hpet specifications ................................................................................................... ....46 table 18. sc04[sci_evt] event sources .....................................................................................51 table 19. system management events ...........................................................................................53 table 20. system power states ................................................................................................... ....58 table 21. resume events ......................................................................................................... .......59 table 22. gpio output clock options ...........................................................................................67 table 23. pci interrupt sources................................................................................................. .....70 table 24. descriptor format ..................................................................................................... ......71 table 25. pcm audio sample order ..............................................................................................72 table 26. maximum valid frame size ...........................................................................................98 table 27. receive statistics counters ........................................................................................... ..99 table 28. transmit statistics counters .........................................................................................1 02 table 29. vlan tag control command......................................................................................106 table 30. vlan tag type ......................................................................................................... ..106 table 31. auto-negotiation capabilities ......................................................................................115 table 32. sources of auto-negotiation advertisement register (r4) bits...................................116 table 33. mac control pause frame format ..............................................................................119 table 34. fccmd bit functions ..................................................................................................1 21 table 35. pause encoding ........................................................................................................ .....122 table 36. format of pmr pointer words .....................................................................................127 table 37. format of pmr data words .........................................................................................127 table 38. arp packet example .................................................................................................... 129 table 39. directed ip packet example..........................................................................................13 0 table 40. nbt name query/registration example .....................................................................130 table 41. pmr programming example ........................................................................................130 12 list of tables AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information table 42. pci configuration spaces .............................................................................................1 36 table 43. pci configuration spaces .............................................................................................1 36 table 44. fixed address spaces .................................................................................................. .137 table 45. relocatable address spaces..........................................................................................13 8 table 46. register behavior types (read, write, etc.)................................................................138 table 47. registers affected by devb:0x41[shen] ...................................................................153 table 48. oarx lock locations ..................................................................................................1 62 table 49. oarx lock bit descriptions ........................................................................................162 table 50. dma controller register summary .............................................................................168 table 51. dma command register bits (master and slave dmac)..........................................168 table 52. dma mode register bits (master and slave dmac).................................................168 table 53. pit register summary.................................................................................................. 169 table 54. pic register summary.................................................................................................. 171 table 55. watchdog timer registers............................................................................................17 5 table 56. hpet registers........................................................................................................ .....177 table 57. smbus status .......................................................................................................... ......201 table 58. device monitor events ................................................................................................. 233 table 59. gpio x[1:0] bit decoding ...........................................................................................245 table 60. gpio register default states........................................................................................24 6 table 61. audio mixer register.................................................................................................. ..256 table 62. audio controller bus master registers ........................................................................258 table 63. modem mixer register .................................................................................................2 67 table 64. modem bus master registers .......................................................................................268 table 65. usb ohci memory-mapped register summary ........................................................277 table 66. receive descriptor bit definitions ...............................................................................347 table 67. transmit descriptor bit definitions..............................................................................350 table 68. absolute ratings ...................................................................................................... .....353 table 69. operating ranges ...................................................................................................... ....354 table 70. current consumption ................................................................................................... .354 table 71. signal groups......................................................................................................... .......355 table 72. dc characteristics for signal group a ........................................................................356 table 73. dc characteristics for signal group c.........................................................................357 table 74. dc characteristics for signal group e ........................................................................357 table 75. dc characteristics for signal group f .......................................................................357 table 76. dc characteristics for signal group g .......................................................................357 table 77. dc characteristics for signal group h ........................................................................358 table 78. ac characteristics for pclk........................................................................................359 table 79. ac characteristics for the osc ....................................................................................359 table 80. ac characteristics for usbclk ..................................................................................360 table 81. alphabetical listing of signals and corresponding bga designators........................362 table 82. pin select options .................................................................................................... .....371 table 83: ...................................................................................................................... .................371 table 84. nand tree 1: output gnt_l[0] ................................................................................371 table 85. nand tree 2: output gnt_l[1] ................................................................................372 list of tables 13 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information table 86. nand tree 3: output nc24 ........................................................................................372 table 87. nand tree 4: output dcstop_l..............................................................................372 table 88. nand tree 5: output diowp_l ................................................................................373 table 89. nand tree 6: output gnt_l[3] ................................................................................373 14 list of tables AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 15 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 16 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information chapter 1 ordering information 17 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information chapter 1 ordering information the ordering part number (opn) is formed by a combination of the elements shown below. contact your amd representative for detailed ordering information. AMD-8111 a c family/core AMD-8111 i/o hub package type a = 492-pin plastic ball grid array c = commercial temperature range case temperature 18 ordering information chapter 1 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information chapter 2 signal descriptions 19 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information chapter 2 signal descriptions 2.1 terminology see section 4.1.2 on page 136 for a description of the register naming conventions used in this document. see section 3.7.1.6 on page 57 for a description of the system power states: moff, soff, std, str, pos, c3, c2, and fon. see section 2.12 on page 34 for a description of the power planes. see section 3.1.1 on page 37 for a description of the types of resets. signals with a _l suf? are active low. signals described in this chapter utilize the following i/o cell types: the following tables provide de?itions and reference data about each pin of the ic. in the table: ? the during reset column provides that state of the pin while the pins power plane is being reset (while reset_l is low for the main power plane; while the internal rst_soft signal is asserted for the aux power plane). ? the after reset column provides the state of the pin immediately after that reset. ? the during pos column provides the state of the pin while in the power on suspend system sleep states. ? the during s3:s5 column provides the state of the pin while in the suspend to disk, suspend to ram, or soft off system sleep states. ? the abbreviation func. means that the signal is functional and operating per its de?ned function. ? the main power plane comprises vdd_io and vdd_core; the aux power plane comprises vdd_iox and vdd_corex. ? the pins are only in a de?ned state when both the speci?ed i/o power plane and the associated core power planes are valid. C pins on the vdd_io power plane are in a de?ned state when vdd_io and vdd_core are valid. table 1. i/o cell types name notes i input signal only. o output signal only. this includes outputs that are capable of being in the high-impedance state. od open drain output. these pins are driven low and expected to be pulled high by external circuitry. io input or output signal. iod input or open-drain output. a analog signal. 20 signal descriptions chapter 2 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information C pins on the vdd_ldt power plane are in a de?ned state when vdd_ldt and vdd_core are valid. C pins on the vdd_iox power plane are in a de?ned state when vdd_iox and vdd_corex are valid. C pins on the vdd_ioal power plane are in a de?ned state when vdd_ioal and vdd_coreal are valid. C pins on the vdd_usb power plane are in a de?ned state when vdd_usb, vdd_usba, and vdd_corex are valid. 2.2 host hypertransport technology interface table 2. host hypertransport technology pin descriptions pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 ldtcomp[3:0]. hypertransport compensation pins. these should be connected as follows: bit function exter nal connection [0] positive rx compensation 50 ohms 10% to vdd_ldt [1] negative rx compensation50 ohms 10% to vss [3:2] tx compensation 100 ohms 1% between ldtcomp[3] and ldtcomp[2] a vdd_ ldt ldtreq_l. hypertransport request to resume pin. external devices assert this pin in order to cause the ic to take the system out of the c3 low-power state. see pm00[bm_sts]. i vdd_ io ldtstop_l. hypertransport disconnect control signal. this is asserted by the ic as speci?d by devb:3x[70, 74, 78]. it is always asserted for a minimum of 1 microsecond. iod vdd_ io 3-state 3-state low ldtrst_l. reset to other hypertransport devices. it is identical to reset_l in timing (but open drain, not push- pull). the logic for this pin includes a debounce circuit. when the signal is asserted high for less than 60 nanoseconds, the debounce logic does not propagate a change of the signal value to the internal logic; the signal must be asserted for at least 90 nanoseconds to be safely detected by the internal logic. i od vdd_ iox low func. func. low lrxcad_h/l[7:0]. hypertransport receive link command- address-data bus. ldt input vdd_ ldt lrxclk_h/l. hypertransport receive link clock. ldt input vdd_ ldt chapter 2 signal descriptions 21 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 2.3 secondary pci interface lrxctl_h/l. hypertransport receive link control signal. ldt input vdd_ ldt ltxcad_h/l[7:0]. hypertransport transmit link command- address-data bus. ldt output vdd_ ldt diff high 1 func. func. ltxclk_h/l. hypertransport transmit link clock. ldt output vdd_ ldt func. func. func. ltxctl_h/l. hypertransport transmit link control signal. ldt output vdd_ ldt diff low 1 func. func. note: 1. diff high and diff low for these hypertransport pins speci?es differential high and low; e.g., diff high means that the _h signal is high and the _l signal is low. table 3. secondary pci interface pin descriptions pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 ad[31:0]. pci address-data bus. some of these pins require pull-up and pull-down resistors for strapping options. see devb:3x48. io vdd_ io 3-state parked parked cbe_l[3:0]. pci command-byte enable bus. io vdd_ io 3-state parked parked devsel_l. pci device select signal. io vdd_ io 3-state 3-state 3-state frame_l. pci frame signal. io vdd_ io 3-state 3-state 3-state gnt_l[6:0]. pci master grant signals. o vdd_ io high high high irdy_l. pci master ready signal. io vdd_ io 3-state 3-state 3-state par. pci parity signal. io vdd_ io 3-state func. func. pclk. 33 mhz pci clock. i vdd_ io perr_l. pci parity error. this signal is only applicable to parity errors on the secondary pci bus interface. this signal is enabled by deva:0x3c[peren]. io vdd_ io 3-state 3-state 3-state pgnt_l. priority pci master grant. see preq_l. o vdd_ io high high high table 2. host hypertransport technology pin descriptions (continued) 22 signal descriptions chapter 2 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 2.4 lpc bus and legacy support pins pirq[a, b, c, d]_l. pci interrupt requests. iod vdd_ io 3-state 3-state func. preq_l. priority pci master request. preq_l/pgnt_l have no functional differences from req_l[6:0]/gnt_l[6:0]. i vdd_ io req_l[6:0]. pci master request signals. i vdd_ io serr_l. pci system error signal. this may be asserted by the system to indicate a system error condition. if enabled by rtc70[7], an nmi interrupt may be generated. i vdd_ io stop_l. pci target abort signal. io vdd_ io 3-state 3-state 3-state trdy_l. pci target ready signal. io vdd_ io 3-state 3-state 3-state table 4. lpc bus and legacy support pin descriptions pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 lad[3:0]. lpc address-data bus. io vdd_ io 3-state 3-state 3-state ldrq_l[1:0]. lpc dma request signals. i vdd_ io lframe_l. lpc frame signal. o vdd_ io high high high osc. 14.31818 mhz clock. this is used for the programmable interval timer and various power management timers. i vdd_ io spkr. speaker driver from programmable interval timer. this pin is an input only while pwrok is low; it is used to select the default state of devb:3x48[12]. io vdd_ io input low last state table 3. secondary pci interface pin descriptions (continued) pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 chapter 2 signal descriptions 23 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 2.5 ultra dma enhanced ide interface 2.6 system management pins this group includes all the gpio pins, most of which are multiplexed with other functions. the default function of gpio pins after reset is speci?d by pm[df:c0]. when programmed as gpios, these pins are capable of being programmed to be inputs or push-pull outputs. gpio pins that are programmed as outputs, remain functional during sleep states if they are powered. table 5. ultra dma enhanced ide pin descriptions pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 daddr[p,s][2:0]. ide controller [primary, secondary] port address. o vdd_ io low low low dcs1p_l. ide controller primary port chip select 1. this is active during accesses to the i/o address space 1f7h?f0h. o vdd_ io high high high dcs1s_l. ide controller secondary port chip select 1. this is active during accesses to the i/o address space 177h 170h. o vdd_ io high high high dcs3p_l. ide controller primary port chip select 3. this is active during accesses to the i/o address space 3f7h?f4h. o vdd_ io high high high dcs3s_l. ide controller secondary port chip select 3. this is active during accesses to the i/o address space 377h 374h. o vdd_ io high high high ddack[p,s]_l. ide controller [primary, secondary] port dma acknowledge signal. o vdd_ io high high high ddata[p,s][15:0]. ide controller [primary, secondary] port data bus. io vdd_ io 3-state 3-state 3-state ddrq[p,s]. ide controller [primary, secondary] port dma request signal. i vdd_ io dior[p,s]_l. ide controller [primary, secondary] port i/o read command. o vdd_ io high high high diow[p,s]_l. ide controller [primary, secondary] port i/o write command. o vdd_ io high high high drdy[p,s]. ide controller [primary, secondary] port ready strobe. i vdd_ io drst[p,s]_l. ide controller [primary ide port reset signal. this is asserted when reset_l is asserted. however, it may be separately asserted through devb:1x54. o vdd_ io low high func. 24 signal descriptions chapter 2 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information table 6. system management pin descriptions pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 acav. ac available input. this may be used to detect changes to the state of system ac power. it controls pm20[acav_sts]. this pin may be con?ured as gpio0 by pmc0. i, io vdd_ iox input input func. func. agpstop_l. agpstop_l is used in support of the acpi c3 and s1 states when an external agp graphics device is used. agpstop_l is asserted during s3/s4/s5. see section 3.7.1.6 on page 57 for agpstop_l sequencing requirements. it is controlled by devb:3x4f[astp_c3en] and devb:3x50[astp]. this pin may be con?ured as gpio1 by pmc1. o, io vdd_ iox high high func. func. batlow_l. battery low input. this may be used to prevent system resumes from sleep states if the battery power is low and ac power is not available. this pin may be con?ured as gpio2 by pmc2. i, io vdd_ iox input input func. func. c32khz. 32.768 khz clock output. this signal is active in all states except moff. this pin may be con?ured as gpio3 by pmc3. o, io vdd_ iox func. func. func. func. clkrun_l. clock run input and open drain output. this signal is de?ed by the pci mobile design guide. it may be used to control the activity of pci clocks. it is available in all power states except str, std, soff, and moff. this pin may be con?ured as gpio5 by pmc5. see pm[df:c0] for the power up defaults of all gpio pins. see section 3.7.1.5 on page 56 for more details. iod, io vdd_ io see left see left func. cpusleep_l. processor non-snoop sleep mode open drain output. this may be connected to the sleep pin of the processor to place it into a non-snoop-capable low-power state. it is controlled by devb:3x4f[cslp_c3en] and devb:3x50[cslp]. this pin may be con?ured as gpio6 by pmc6. see pm[df:c0] for the power up defaults of all gpio pins. od, io vdd_ io see left see left func. cpustop_l. processor clock stop output. this may be connected to the system clock chip to control the host clock signals. it is controlled by devb:3x50[cstp]. this pin may be con?ured as gpio7 by pmc7. o, io vdd_ io high high func. dcstop_l. dram controller stop. this may be connected to the system memory controller to indicate that its clock is going to stop. it is controlled by devb:3x50[dcstp]. also see section 3.7.1.6 on page 57 for a description of dcstop_l during acpi state transitions. o vdd_ iox func. func. func. func. extsmi_l. external smi. this pin may be used to generate smi or sci interrupts and resume events. it controls pm20[extsmi_sts]. i vdd_ iox chapter 2 signal descriptions 25 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information fancon[1:0]. fan control outputs. these may be used to control system fans. the frequency and duty cycle are speci?d by pmf8. fancon1 may be con?ured as gpio9 by pmc9. o, io vdd_ io low func. func. fanrpm. fan revolutions per minute input. this may come from the system power supply. it is expected that it represents 2 pulses per fan revolution. pm1f, which is a counter that is clocked by this signal, can be used to determine the speed of the fan. this pin may be con?ured as gpio10 by pmca. i, io vdd_ io gpio14. general purpose i/o 14. this is controlled by pmce. see pm[df:c0] for the power up defaults of all gpio pins. io vdd_ iox see left see left func. func. gpio[31:26, 17, 16, 8, 4]. general purpose i/o. these are controlled by pm[df:c0]. see pm[df:c0] for the power up defaults of all gpio pins. nmi#. see pm[df:c0] for the power up defaults and functional description. io vdd_ io see left see left func. intirq8_l. real-time clock interrupt output. this is real- time clock interrupt. this pin may be con?ured as gpio11 by pmcb. o, io vdd_ io high high func. intruder_l. intruder detection. this controls pm46[intrdr_sts]. i vdd_ ioal irq1. keyboard interrupt request input. this pin may be con?ured as gpio12 by pmcc. i, io vdd_ io irq6. floppy disk controller interrupt request input. this pin may be con?ured as gpio13 by pmcd. i, io vdd_ io irq12. mouse interrupt request input. this pin may be con?ured as gpio15 by pmcf. i, io vdd_ io irq14. ide primary port interrupt request. i vdd_ io irq15. ide secondary port interrupt request. i vdd_ io ka20g. keyboard a20 gate. this is expected to be the gate a20 signal from the system keyboard controller. it affects a20m_l. i vdd_ io kbrc_l. keyboard reset command. this is expected to be the processor reset signal from the system keyboard controller. when asserted, it generates an init interrupt to the processor. i vdd_ io table 6. system management pin descriptions (continued) pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 26signal descriptions chapter 2 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lid. lid change-state detect input. this may be used to detect state changes in notebook shell lids. the logic for this pin includes a debounce circuit. when the signal is asserted high or low for less than 12 milliseconds, the debounce logic does not propagate a change of the signal value to the internal logic; the signal must be asserted for at least 16 milliseconds to be safely detected by the internal logic. this pin may be con?ured as gpio18 by pmd2. i, io vdd_ iox pcistop_l. pci bus clock stop. this may be used to control the system clock chip to control the pci bus clock signals. it is controlled by devb:3x50[pstp]. it may also be used in association with clkrun_l; see section 3.7.1.5 on page 56 for more details. o vdd_ io high high func. pme_l. power management interrupt. this pin may be used to generate smi or sci interrupts and resume events. it controls pm20[pme_sts]. i vdd_ iox pnpirq[2:0]. plug and play interrupt request inputs. these may be assigned to control any of 12 of the internal irq signals by devb:3x44. pnpirq0 may be con?ured as gpio19 by pmd3; pnpirq1 may be con?ured as gpio20 by pmd4; pnpirq2 may be con?ured as gpio21 by pmd5. i, io, vdd_ io input input input prdy. processor ready. when this is asserted, the ic freezes the timers speci?d by devb:3x4c. i vdd_ io pwrbtn_l. power button. this may be used to control the automatic transition from a sleep state to fon. it controls pm00[pwrbtn_sts]. also, if it is asserted for four seconds from any state other than soff, then a power button override event is generated. a power button override event causes the pwron_l pin to be driven high and pm00[pbor_sts] to be set high. the logic for this pin includes a debounce circuit. when the signal is asserted high or low for less than 12 milliseconds, the debounce logic does not propagate a change of the signal value to the internal logic; the signal must be asserted for at least 16 milliseconds to be safely detected by the internal logic. i vdd_ iox table 6. system management pin descriptions (continued) pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 chapter 2 signal descriptions 27 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information pwrok. power ok. this is required to be low while the main power planes are not valid, stay low for at least 50 milliseconds after they become valid, and then go high. it is the reset source for the main power supplies of the ic, vdd_core and vdd_io. the logic for this pin includes a debounce circuit. when the signal is asserted high for less than 30 microseconds, the debounce logic does not propagate a change of the signal value to the internal logic; the signal must be asserted for at least 60 microseconds to be safely detected by the internal logic. i vdd_ iox pwron_l. main power on. this is expected to control the main power supplies to the system board. it is asserted during the fon, c2, c3, and pos states; it is deasserted during the str, std and soff states. when power is applied to the aux plane, this signal is forced inactive until rst_soft is deasserted. see section 3.7.1.6.2 on page 60 for more details. od vdd_ iox 3-state low low 3-state reset_l. system reset. this is the system reset signal for logic that is powered by the main power supplies. see section 3.1.1 on page 37 and section 3.7.1.6.2 on page 60 for more details. o vdd_ iox func. func. high low ri_l. ring indicate. this is intended to cause the system to resume to the fon states and generate sci or smi interrupts. it controls pm20[ri_sts]. i vdd_ iox rpwron. ram power on. this is intended to control power to the system memory power plane. when high, it is expected that power to system memory is enabled. when low, it is expected that power to system memory is disabled. this pin is low during std and soff and high in all other states. see section 3.7.1.6.2 on page 60 for more details. od vdd_ iox func. 3-state 3-state func. rtcx_in. real-time clock 32.768 khz crystal input. this pin is expected to be connected through a crystal oscillator to rtcx_out. a vdd_ ioal func. func. func. func. rtcx_out. real-time clock 32.768 khz crystal output. a vdd_ ioal func. func. func. func. s3pll_lf. s3pll external loop ?ter pin. a vdd_ iox func. func. func. func. s3pll_lf_vss. s3pll external loop ?ter pin. a vdd_ iox func. func. func. func. serirq. serial irq signal. this pin supports the serial irq protocol. control for this is in devb:3x4a. io vdd_ io 3-state 3-state func. table 6. system management pin descriptions (continued) pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 28 signal descriptions chapter 2 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information slpbtn_l. sleep button input. this may be used to control the automatic transition from a sleep state to fon. it controls pm00[slpbtn_sts]. also, if it is asserted for four seconds from any state other than soff, then a power button override event is generated. a power button override event causes the pwron_l pin to be driven high and pm00[pbor_sts] to be set high. the logic for this pin includes a debounce circuit. when the signal is asserted high or low for less than 12 milliseconds, the debounce logic does not propagate a change of the signal value to the internal logic; the signal must be asserted for at least 16 milliseconds to be safely detected by the internal logic. this pin may be con?ured as gpio23 by pmd7. i, io vdd_ iox smbalert0_l. smbus 1.0 alert input. this may be used to generate an smi or sci interrupt or a resume event associated with the smbus logic. this pin may be con?ured as gpio22 by pmd6. note: although this pin resides on the vdd_iox power plane, it can only be used for the smbus alert function while the main power supply is valid. i, io vdd_ iox smbalert1_l. smbus 2.0 alert input. this may be used to generate an smi or sci interrupt or a resume event associated with the smbus logic. this pin may be con?ured as gpio24 by pmd8. i, io vdd_ iox smbusc[1:0]. system management bus (smbus) clock. smbusc[0] is associated with the smbus 1.0 host controller and smbusc[1] is associated with the smbus 2.0 host controller. the logic for the smbusc1 pin includes a debounce circuit. when the signal is asserted high or low for less than 80 nanoseconds, the debounce logic does not propagate a change of the signal value to the internal logic; the signal must be asserted for at least 100 nanoseconds to be safely detected by the internal logic. iod vdd_ iox 3-state 3-state func. func. smbusd[1:0]. system management bus (smbus) data. smbusd[0] is associated with the smbus 1.0 host controller and smbusd[1] is associated with the smbus 2.0 host controller. the logic for the smbusd1 pin includes a debounce circuit. when the signal is asserted high or low for less than 80 nanoseconds, the debounce logic does not propagate a change of the signal value to the internal logic; the signal must be asserted for at least 100 nanoseconds to be safely detected by the internal logic. iod vdd_ iox 3-state 3-state func. func. table 6. system management pin descriptions (continued) pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 chapter 2 signal descriptions 29 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 2.7 universal serial bus interface suspend_l. this may be used to gate reset_l during suspend to ram (s3) or to enable power reduction during power on suspend (s1). it is controlled by devb:3x50[susp]. this pin may be con?ured as gpio25 by pmd9. o, io vdd_ iox high high func. therm_l. thermal warning detect. this may be used to automatically enable processor throttling as speci?d by devb:3x4d[tth_ratio, tth_en, tth_lock]. this pin is also controlled by devb:3x40[th2sd, ttper, thminen] and devb:3x70[ttls, ttsmaf], see also pm20[therm_sts], pm22[therm_en], pm2a[thmsmi], pmf8[fc[1:0]therm]. see section 3.7.1.4 on page 56 for more details. i vdd_ io thermtrip_l. processor thermal trip point exceeded. when asserted while pwron_l =0, pwrok=1, and reset_l= 1 the ic sets pm46[tt_sts] and forces the system to s5. the logic for this pin includes a debounce circuit. when the signal is asserted low for less than 960 nanoseconds, the debounce logic does not propagate a change of the signal value to the internal logic; the signal must be asserted for at least 990 nanoseconds to be safely detected by the internal logic. i vdd_ io table 7. usb pin descriptions pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 usbclk. 48 mhz usb clock. i vdd_ io usb0_h/l[2:0]. usb hub 0 ports. these are the three pairs of differential usb signals. usb0p[2:0] are the positive signals and usb0n[2:0] are the negative signals. io vdd_ usb low low 3- state; can detect resume 3- state; can detect resume usb1_h/l[2:0]. usb hub 1 ports. these are the three pairs of differential usb signals. usb1p[2:0] are the positive signals and usb1n[2:0] are the negative signals. io vdd_ usb low low 3- state; can detect resume 3- state; can detect resume table 6. system management pin descriptions (continued) pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 30 signal descriptions chapter 2 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 2.8 ac ?7 interface usboc0_l. usb over current detect 0. this goes to the usb logic to report the occurrence of an over-current condition on the voltage supplied to the usb ports. i vdd_ io usboc1_l. usb over current detect 1. when enabled to do so, this can be routed to the usb block to be a second source of usb port over-current detection. i vdd_ io usb_rext. usb phy external resistor. this signal connects to an external resistor. the resistor should be 3.09 kohm with a tolerance of 1% across the 0 c to +125 c temperature range. a vdd_ usb table 8. ac ?7 pin descriptions pin name and description i/o cell type power plane during reset after reset during pos during s3:s5 acclk. ac ?7 bit clock. 12.288 mhz ?ed frequency from primary codec. an external 10-kohm pull-down resistor is required on this pin in support of powering down the ac-link codec. i vdd_ io acrst_l. ac ?7 asynchronous reset. o vdd_ iox low low low low acsdi0. ac ?7 primary codec serial data in (slot 0 codec id ?ld = 00b) from ?st codec in system. an external 10-kohm pull-down resistor is required on this pin in support of powering down the ac-link codec. i vdd_ iox can detect resume can detect resume acsdi1. ac ?7 secondary codec serial data in (slot 0 codec id ?ld = 01b) from second codec in system. an external 10- kohm pull-down resistor is required on this pin in support of powering down the ac-link codec. i vdd_ iox can detect resume can detect resume acsdo. ac ?7 serial data out. o vdd_ io low low low acsync. ac ?7 frame synchronization pulse. o vdd_ io low low low table 7. usb pin descriptions (continued) chapter 2 signal descriptions 31 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 2.9 mii interface table 9. mii interface pin descriptions pin name and description i/o cell type power plane during reset after reset during s1:s2 during s3:s5 mii_tx_clk. mii transmit clock. mii_tx_clk is a continuous clock input that provides the timing reference for the transfer of the mii_tx_en and mii_txd[3:0] signals. mii_tx_clk must provide a nibble rate clock (25% of the network data rate). hence, an mii transceiver operating at 10 mbit/s must provide a mii_tx_clk frequency of 2.5 mhz and an mii transceiver operating at 100 mbit/s must provide a mii_tx_clk frequency of 25 mhz. i vdd_ iox mii_txd[3:0]. mii transmit data. mii_txd[3:0] is the nibble-wide mii transmit data bus. valid data is generated on mii_txd[3:0] on every mii_tx_clk rising edge while mii_tx_en is asserted. while mii_tx_en is deasserted, mii_txd[3:0] values are driven low. mii_txd[3:0] transitions synchronous to mii_tx_clk rising edges. o vdd_ iox low low func. func. mii_tx_en. mii transmit enable. mii_tx_en indicates when valid transmit nibbles are presented on the mii. while mii_tx_en is asserted, mii_txd[3:0] data are generated on mii_tx_clk rising edges. mii_tx_en is asserted with the ?st nibble of preamble and remains asserted throughout the duration of a packet until it is deasserted prior to the ?st mii_tx_clk following the ?al nibble of the frame. mii_tx_en transitions synchronous to mii_tx_clk rising edges. o vdd_ iox low low func. func. mii_col. mii collision. mii_col is an input that indicates that a collision has been detected on the network medium. i vdd_ iox mii_crs. mii carrier sense. mii_crs is an input that indicates that a non-idle medium, due either to transmit or receive activity, has been detected. i vdd_ iox mii_rx_clk. mii receive clock. mii_rx_clk is a clock input that provides the timing reference for the transfer of the mii_rx_dv, mii_rxd[3:0], and mii_rx_er signals. mii_rx_clk must provide a nibble rate clock (25% of the network data rate). hence, an mii transceiver operating at 10 mbit/s must provide an mii_rx_clk frequency of 2.5 mhz and an mii transceiver operating at 100 mbit/s must provide an mii_rx_clk frequency of 25 mhz. when the external phy switches the mii_rx_clk and mii_tx_clk, it must provide glitch-free clock pulses. i vdd_ iox 32 signal descriptions chapter 2 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information mii_rxd[3:0]. mii receive data. mii_rxd[3:0] is the nibble-wide mii receive data bus. data on mii_rxd[3:0] is sampled on every rising edge of mii_rx_clk while mii_rx_dv is asserted. mii_rxd[3:0] is ignored while mii_rx_dv is de-asserted. i vdd_ iox mii_rx_dv. mii receive data valid. mii_rx_dv is an input used to indicate that valid received data is being presented on the mii_rxd[3:0] pins and mii_rx_clk is synchronous to the receive data. in order for a frame to be fully received on the mii, mii_rx_dv must be asserted prior to the mii_rx_clk rising edge, when the ?st nibble of the start of frame delimiter is driven on mii_rxd[3:0], and must remain asserted until after the rising edge of mii_rx_clk, when the last nibble of the mii_crc is driven on mii_rxd[3:0]. mii_rx_dv must then be deasserted prior to the mii_rx_clk rising edge which follows this ?al nibble. mii_rx_dv transitions are synchronous to mii_rx_clk rising edges. i vdd_ iox mii_rx_er. mii receive error. mii_rx_er is an input that indicates that the mii transceiver device has detected a coding error in the receive frame currently being transferred on the mii_rxd[3:0] pins. when mii_rx_er is asserted while mii_rx_dv is asserted, a mii_crc error is indicated in the receive descriptor for the incoming receive frame. mii_rx_er is ignored while mii_rx_dv is deasserted. special code groups generated on mii_rxd while mii_rx_dv is deasserted are ignored (e.g., bad ssd in tx and idle in t4). mii_rx_er transitions are synchronous to mii_rx_clk rising edges. i vdd_ iox table 9. mii interface pin descriptions (continued) pin name and description i/o cell type power plane during reset after reset during s1:s2 during s3:s5 chapter 2 signal descriptions 33 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 2.10 test mii_phy_rst. mii phy reset. mii_phy_rst is an output pin that is used to reset the external phy. the output polarity is determined by enc054[phy_rst_pol]. o vdd_ iox low low func. func. mii_mdc. mii management data clock. mii_mdc is a non-continuous clock output that provides a timing reference for bits on the mii_mdio pin. during mii management port operations, mii_mdc runs at a nominal frequency of 2.5 mhz. when no management operations are in progress, mii_mdc is driven low. if the mii management port is not used, the mii_mdc pin can be left ?ating. o vdd_ iox low low func. func. mii_mdio. mii management data i/o. mii_mdio is the bidirectional mii management port data pin. mii_mdio is an output during the header portion of the management frame transfers and during the data portions of write transfers. mii_mdio is an input during the data portions of read data transfers. when an operation is not in progress on the management port, mii_mdio is not driven. mii_mdio transitions are synchronous to mii_mdc falling edges. if the phy is attached through an mii physical connector, then the mii_mdio pin should be externally pulled low with a 10-kohm 5% resistor . if the phy is permanently connected, then the mii_mdio pin should be externally pulled high with a 10-kohm 5% resistor . io vdd_ iox func. func. table 10. test pin descriptions pin name and description i/o cell type power plane during reset after reset during s1:s2 during s3:s5 test_l. scan, nand tree, and high-impedance mode enable. i vdd_ io table 9. mii interface pin descriptions (continued) pin name and description i/o cell type power plane during reset after reset during s1:s2 during s3:s5 34 signal descriptions chapter 2 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 2.11 miscellaneous 2.12 power and ground see section 3.7.1.6 on page 57 for a description of the system power states. the following power and ground planes are connected to the ic through bga pins. vdd_io. 3.3-v supply. this plane is required to be valid in the fon and pos power states. it is part of the main power supply. vdd_core. 1.8-v supply. this plane is required to be valid in the fon and pos power states. it is part of the main power supply. vdd_iox and vdd_corex. vdd_iox is a 3.3-v plane and vdd_corex is a 1.8-v plane. both of these planes are required to be valid at the same times. they are valid in all system power states except moff. both power planes are part of the aux power supply. register bits that are on the vdd_corex plane are reset by the internal rst_soft pulse that is generated for about 30 milliseconds after vdd_corex becomes valid. vdd_ldt. 1.2-v hypertransport link reference voltage. this plane is required to be valid in the fon and pos power states. it is part of the main power supply. vdd_ref. 5.0-v reference supply. this plane is required to be valid in all power states except moff. it is part of the aux power supply. vdd_rtc. 3.3-v supply. this plane is required to be valid in all power states. it is typically powered by a battery. it supplies power for the internal al power plane when aux is not valid. vdd_usb. 3.3-v supply ?tered for the usb transceivers. this plane is required to be valid in all power states except moff. vdd_usba. 1.8-v supply ?tered for the usb transceivers. this plane is required to be valid in all power states except moff. vss. main ground plane. vss_usba. ground plane ?tered for the usb transceivers. the ic also includes the following two internal power planes. table 11. miscellaneous pin descriptions pin name and description i/o cell type power plane during reset after reset during s1:s2 during s3:s5 nc[32:0]. must be left unconnected. straph[3:0]. must be tied high. strapl[3:0]. must be tied low. chapter 2 signal descriptions 35 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information vdd_ioal and vdd_coreal. vdd_ioal is a 3.3-v plane and vdd_coreal is a 1.8-v plane. both power planes are part of the internal al (always) power plane. al is supplied by aux when that plane is valid or by vdd_rtc when aux is not valid. al powers the real-time clock and some system management circuitry. general requirements: ? the voltage level of vdd_core is required to be less than vdd_io at all times. ? the voltage level of vdd_corex is required to be less than vdd_iox at all times. ? the voltage level of vdd_io and vdd_iox is required to be less than vdd_ref at all times. ? vdd_corex, vdd_iox and vdd_ref are required to be powered before vdd_core and vdd_io may be powered. 36signal descriptions chapter 2 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information chapter 3 functional operation 37 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information chapter 3 functional operation 3.1 o verview 3.1.1 resets the ic generates an internal reset for the aux power planes called rst_soft. rst_soft lasts for about 30 milliseconds after the aux planes become valid. pwrok is the source of reset for the vdd_io and vdd_core logic on the ic. from this signal, reset_l, init_l and ldtrst_l are derived. it is possible to generate a reset to the system through devb:0x47[swrst]. these cause reset_l and ldtrst_l to be asserted for greater than 1.5 milliseconds. various system resets are also possible through portcf9. it is also possible to generate a reset to the processor (without clearing the cache) with init interrupt through the external keyboard controller using kbrc_l, the port92 register, or from a shutdown command from the host. 3.1.2 error reporting and handling the following is a summary of the errors that are reported and how they are handled in the ic; secondary refers to the secondary side of the pci bridge, which includes an external pci bus, the two usb controllers and the ethernet controller. table 12. error handling error type status bit handler enable handler action notes received target abort on host deva:0x04[rta] devb:0x40[nmionerr] generate nmi received master abort on host deva:0x04[rma] devb:0x40[nmionerr] generate nmi host bus crc error deva:0xc4[lkfail] deva:0xc4[crcfen] flood outgoing hypertransport link with sync packets 1 deva:0xc4[crcerr] devb:0x40[nmionerr] generate nmi 3 link incoming sync ?od is detected none devb:0x47[rstonle] system reset 1 signaled target abort on secondary bus deva:0x1c[sta] devb:0x40[nmionerr] generate nmi received target abort on secondary bus deva:0x1c[rta] devb:0x40[nmionerr] generate nmi 3 38 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information received target abort on secondary bus while executing a downstream posted command deva:0x1c[rta] devb:0x40[serren] flood outgoing hypertransport link with sync packets 1 received master abort on secondary bus deva:0x1c[rma] devb:0x40[nmionerr] generate nmi 3 received master abort on secondary bus while executing a downstream posted command deva:0x1c[rma] devb:0x40[serren] deva:0x3c[marsp] flood outgoing hypertransport link with sync packets 1 serr_l assertion detected deva:0x1c[rse] devb:0x40[nmionerr] generate nmi 3 port61[serr] port61[clrserr] generate nmi 3 deva:0x1c[rse] deva:0x04[serren] deva:0x3c[serren] flood outgoing hypertransport link with sync packets 1 detected data parity error on secondary bus while receiving data as master or target dev:0x1c[dpe] devb:0x40[nmionerr] generate nmi; assert perr_l if target 2 detected data parity error on secondary bus while receiving data as master dev:0x1c[mdpe] deva:0x3c[peren] generate nmi detected address parity error during cycle from external master deva:0x1c[dpe] deva:0x04[serren] deva:0x3c[serren] deva:0x3c[peren] flood outgoing hypertransport link with sync packets 1 perr_l assertion detected while sending data as master deva:0x1c[mdpe] deva:0x3c[peren] generate nmi 3 perr_l assertion detected while sending posted data as master deva:0x1c[mdpe] deva:0x3c[peren] deva:0x04[serren] flood outgoing hypertransport link with sync packets 1 secondary discard timer expires deva:0x3c[dtstat] devb:0x40[nmionerr] generate nmi 3 deva:0x3c[dtstat] deva:0x3c[dtserren] deva:0x04[serren] flood outgoing hypertransport link with sync packets 1 table 12. error handling (continued) error type status bit handler enable handler action notes chapter 3 functional operation 39 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 3.1.3 clocks the ic includes the following clocks on its pins. 3.2 host interface 3.2.1 hypertransport technology host interface the hypertransport technology interface provides the host connection for the ic. the link supports up to 800 megabytes per second of total bandwidth. the hypertransport input and output links support multiple bit widths, including 8, 4, and 2 bits, with a 200 mhz hypertransport clock. 3.2.1.1 hypertransport protocol unit ids the hypertransport protocol unit id values are assigned by the platform designer by programming deva:0xc0[buid]. lpc protocol error devb:0x40[lpcerr], port61[iochk] port61[clriochk] generate nmi received posted write targeting lpc while lpc bus master is active devb:0x40[pw2lpc] devb:0x40[nmionerr] generate nmi notes: 1. the link is ?ooded with sync packets and deva:0x04 gets set. system reset is possible when setting devb:0x47[rstonle].. 2. perr_l is only asserted if it is enabled by deva:0x3c[peren]. 3. if both sync ?od and nmi are enabled then the nmi will not reach the host because the link gets ?oded before. table 13. ic clock pins name pin type description osc input 14.31818 mhz. this is used by the legacy programmable interval timer (pit) and by some of the power management logic. pclk input up-to 33.333 mhz pci clock. usbclk input 48 mhz. this is used by the usb controller. rtc_xin, rtc_xout oscillator 32.768 khz oscillator pair. the clock generated by this oscillator is used by the real time clock and by some of the system management logic; it is powered by vdd_ioal. acclk input 12.288 mhz. this is used as serial input clock for ac ?7. mii_rxclk input 2.5 or 25 mhz. this is the receive clock from ethernet phy0 mii_txclk input 2.5 or 25 mhz. this is the transmit clock from ethernet phy0 table 12. error handling (continued) error type status bit handler enable handler action notes 40 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.3 secondary pci bridge the secondary pci bridge interfaces to the internal usb and ethernet controllers and the external pci bus. peer to peer transactions are supported between devices on the external pci bus. however, all other transactions pass through the host interface; peer to peer transactions between internal and external devices are not supported. 3.4 lpc bridge and legacy logic the lpc bridge supports external peripherals and bios devices through the lpc bus. it also includes legacy devices and logic required for compatibility with existing software. 3.4.1 legacy and miscellaneous support logic the ic includes the following legacy support logic: ? port61 and port92 legacy registers. ? ferr_l and ignne interrupt logic. ? port4d0 legacy interrupt edge-level select logic. ? portcf9 reset logic. ? legacy dual-8237 dma controller. ? legacy 8254 pit. 3.4.2 interrupt controllers interrupt types include vectored interrupts?ntr, extint, ?ed, and lowest priority?nd non- vectored interrupts nmi, smi, and init. based on devb:0x4b[apicen], these are sent through routing equations, the legacy pic, and the ioapic to be transmitted to the host through hypertransport messages. as hypertransport messages, they can be sourced from either the internal ioapic or other internal hypertransport interrupt message logic (see figure 2). table 14. hypertransport protocol unit ids unit unit id data associated with unit id first buid pci (all functions except ide) second buid + 1 ide primary port third buid + 2 ide secondary port fourth buid + 3 ehci-based usb controller chapter 3 functional operation 41 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 2. interrupt sources the following table speci?s how interrupts are routed based on the con?uration bit. 3.4.2.1 interrupt control and routing vectored interrupt requests are routed to the legacy pic and apic as shown in figure 3. the interrupt signals to the pic can be either rising-edge triggered or active-low level triggered. it is expected that edge-triggered interrupts such as irq14 from the ide controller rise into the pic to indicate the presence of an interrupt. conversely, level-sensitive interrupts are low into the pic to indicate the presence of an interrupt. edge and level sensitivity for each irq are programmed into the pic through port4d0. table 15. interrupt routing con?uration apic-en interrupt delivery mechanisms. 0 hypertransport interrupt message logic is used to send all interrupt requests. 1 interrupts from the ioapic and internally generated non-vectored interrupts are translated into hypertransport interrupt request messages. hypertransport hypertransport interrupt message logic legacy dual-8259 pic interrupt routing equation ioapic 24-entry redirection table intr gpio[31:28] pirq[a,b,c,d]_l irq pins, tco, pnpirq[2:0], irq8, irq13, serial irq, sci nmi, init, smi interrupt request 42 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information figure 3. vectored interrupt routing several internal interrupts are shared with the pci interrupts pins. these internal interrupt signals drive the pirq[a,b,c,d]_l pins low as outputs; when the internal interrupts are deasserted, the pins are left in the high impedance state. these pins are wire-ored into the active state with external interrupts. the result enters the ic and goes to the interrupt routing logic. the internal interrupts are mapped to the pirq[a,b,c,d]_l pins as follows: ? gpio[31:28] can be speci?ed by devb:0x4b[mpirq] to drive onto pirq[a,b,c,d]_l, respectively. ? the ethernet controller interruptlanc_intdrives onto the pirqa_l pin. ? the primary and secondary port, when these ports are in native mode, ide controller interrupts nmp_int, nms_intdrive onto the pirqa_l pin. ? the ac 97 interruptac97_intdrives onto the pirqb_l pin. ? the usb controller interruptsusb0_int, usb1_int, ehc_intdrives onto the pirqd_l pin. ? the smbus 2.0 controller interruptsmbc_intdrives onto the pirqd_l pin. alternatively, these interrupts may all be mapped to pirqd_l, as speci?d by devb:0x47[alltod]. here are the interrupt routing logic equations: pirq_pola = ~pirqa_l | serinta; pirq_polb = ~pirqb_l | serintb; pirq_polc = ~pirqc_l | serintc; pirq_pold = ~pirqd_l | serintd; pci_irqx = pirq_pola & (devb:3x56[3:0] == 4'hx) | pirq_polb & (devb:3x56[7:4] == 4'hx) | pirq_polc & (devb:3x56[11:8] == 4'hx) | pirq_pold & (devb:3x56[15:12] == 4'hx); interrupt routing logic ioapic port4d0 pic pirq[a,b,c,d]_l pnpirq[2:0] sci_irq irqx pins, devices serial irqs lanc_int, smbc_int, usb0_int, usb1_int, ehc_int, ac97_int, gpio[31:28], nmp_int, nms_int chapter 3 functional operation 43 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information pnp_irqx = pnpirq2 & (devb:3x44[11:8] == 4'hx) | pnpirq1 & (devb:3x44[7:4] == 4'hx) | pnpirq0 & (devb:3x44[3:0] == 4'hx); sci_irqx = sci_irq & (devb:3x42[3:0] == 4'hx); isa_irqx = ~(irqx & serirqx ) & ~( (devb:3x56[3:0] == 4'hx) | (devb:3x56[7:4] == 4'hx) | (devb:3x56[11:8] == 4'hx) | (devb:3x56[15:12] == 4'hx) | (devb:3x44[11:8] == 4'hx) | (devb:3x44[7:4] == 4'hx) | (devb:3x44[3:0] == 4'hx) | (devb:3x42[3:0] == 4'hx) ); kirq1 = irq1 & serirq1; // to the usb keyboard emulation logic kirq12 = irq12 & serirq12; // to the usb keyboard emulation logic usb0_irq1 = ~externalirqen & kirq1 // signal names from usb ohci spec | emulationenable & irqen & outputfull & ~auxoutputfull; usb0_irq12 = ~externalirqen & kirq12 // signal names from usb ohci spec | emulationenable & irqen & outputfull & auxoutputfull; isa_irq1 = ~(usb0_irq1) & ~( (devb:3x56[3:0] == 4'h1) | (devb:3x56[7:4] == 4'h1) | (devb:3x56[11:8] == 4'h1) | (devb:3x56[15:12] == 4'h1) | (devb:3x44[11:8] == 4'h1) | (devb:3x44[7:4] == 4'h1) | (devb:3x44[3:0] == 4'h1) | (devb:3x42[3:0] == 4'h1); isa_irq12 = ~(usb0_irq12) & ~( (devb:3x56[3:0] == 4'hc) | (devb:3x56[7:4] == 4'hc) | (devb:3x56[11:8] == 4'hc) | (devb:3x56[15:12] == 4'hc) | (devb:3x44[11:8] == 4'hc) | (devb:3x44[7:4] == 4'hc) | (devb:3x44[3:0] == 4'hc) | (devb:3x42[3:0] == 4'hc); isa_irq14 = ~(irq14 & serirqe ) & ~( (devb:3x56[3:0] == 4'he) | (devb:3x56[7:4] == 4'he) | (devb:3x56[11:8] == 4'he) | (devb:3x56[15:12] == 4'he) | (devb:3x44[11:8] == 4'he) | (devb:3x44[7:4] == 4'he) | (devb:3x44[3:0] == 4'he) | (devb:3x42[3:0] == 4'he) | devb:1x08[8]); isa_irq15 = ~(irq15 & serirqf ) & ~( (devb:3x56[3:0] == 4'hf) | (devb:3x56[7:4] == 4'hf) | (devb:3x56[11:8] == 4'hf) | (devb:3x56[15:12] == 4'hf) | (devb:3x44[11:8] == 4'hf) | (devb:3x44[7:4] == 4'hf) | (devb:3x44[3:0] == 4'hf) | (devb:3x42[3:0] == 4'hf) | devb:1x08[10]); pic_irqx = ~(isa_irqx | pci_irqx | pnp_irqx | sci_irqx ); nmp_int = devb:1x08[8] & irq14; nms_int = devb:1x08[10] & irq15; where: x the pic irq number, 1, 3?, 9?2, 14, and 15. pirq[a,b,c,d]_l the input pci interrupts (with the polarity of the external signals). serint[y] the pci interrupts captured from the serirq pin (with the same polarity as the serirq pin). serirq[x] the isa interrupts captured from the serirq pin (with the same polarity as the serirq pin). usb0_irq[12,1] outputs of the keyboard emulation logic from the usb controller. ekirq[12,1] external keyboard controller's interrupts from irq1 and irq12 when the interrupt function is selected by gpio12 and gpio15. 44 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information pnpirq[2:0] pnp irq pins (with the polarity speci?d by the associated gpio control register). sci_irq active-high sci interrupt. irqx external interrupt. pic_irqx the interrupt signals that go to the pic. notes from the interrupt routing equations: ? when a pci, pnp, or sci interrupt is enabled onto a pic_irq, then the external and serial irq capability for the irq is disabled. ? external irqs and serial irqs are expected to be edge triggered. ? pci pin and sci interrupts are intended to be level triggered. ? pnp interrupts can be level or edge triggered. the inverter available in the gpio control register must be used to preserve the polarity from the external signal to the pic; if this inverter is not selected, then there is an inversion from the external signal to the pic. ? irq14 and irq15 change from external interrupts to native mode interrupts driven by the ide drives if devb:1x08[8 and 10] are set respectively. as native mode interrupts, they are still expected to be active high (externally); they are combined with pirqa_l logic to become level- triggered, active low signals into the pic. ? the keyboard and mouse interrupt pins, irq1 and irq12, are anded with the serial irq versions to go to the usb keyboard emulation logic. the outputs of this logic enter the routing equations. ? in order for the usb keyboard and mouse emulation interrupts to function properly, either the irq1 and irq12 pins must be strapped low or an external keyboard controller must keep the serial irq slots for irq1 and irq12 low. 3.4.2.2 pic/smi/nmi/init to hypertransport link translation traditionally, processors have treated smi, nmi, and init as edge triggered interrupts and intr as a level triggered interrupt. the pic, however, is required to generate an edge on its output intr signal for each interrupt. therefore, it too can be treated like it is edge triggered. smi, nmi, and init all behave the same way. when an active-going edge is detected on the internal version of these signals, the ic generates the appropriate interrupt message to the host. in order for another interrupt to occur, the signal must be deasserted and then asserted again (matching the historical edge-sensitive behavior of these signals). for these messages, mt = smi, nmi, or init (as appropriate), tm = edge, dm = physical; intrdest = 'hff (all); and vector = 'h00 (does not matter). when the pic detects an interrupt, it asserts its internal intr signal. if the ioapic is enabled, then this intr signal is ignored by the hypertransport interrupt message logic (with the expectation that the equivalent interrupt will be generated by the ioapic). otherwise, when intr is asserted, the ic generates an interrupt request hypertransport message as follows: mt = extint; tm = edge; dm = physical; intrdest = 'hff (all); vector = 'h00 (does not matter). the host responds with an chapter 3 functional operation 45 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information interrupt acknowledge message to the pic. the interrupt vector is in the 8 lsbs of the response and the 24 msbs are zero. the pic clears the intr line for a minimum of one pclk when the interrupt acknowledge is received. 3.4.2.3 ioapic the ioapic supports 24 interrupt signals which come from the interrupt routing logic, the pci interrupts, gpios, and internal signals. based on con?uration, it sends interrupt messages through the hypertransport bus. 3.4.2.3.1 ioapic redirection registers the ioapic supports 24 interrupt request signals. each interrupt request input is combined with its corresponding redirection register to specify the behavior of the interrupt. these interrupt request signals are connected to redirection registers (apic irqs) as shown in the following table. see section 3.4.2.1 on page 41 for the de?ition of the ?ic irq signals. see devb:0x4b[mpirq] for a description of how the mask bits from redirection table entries[23:20] can affect the routing of gpio[31:28] onto pirq[a,b,c,d]_l. see devb:3x44[tco_int_sel] for a description of how other interrupts may be directed to the ioapic. 3.4.2.4 nmi nmi is controlled as described in the following equation: nmi = ~port70[nmidis] & ( pm48[nmi_now] | ~pm48[nmi2smi_en] & ( port61[serr] & ~port61[clrserr] | port61[iochk] & ~port61[clriochk] | devb:0x40[nmionerr] & [status bits described in section 3.1.2] | deva:0x1c[mdpe] & deva:0x3c[peren] ) ); table 16. ioapic redirection register connections apic irq connection apic irq connection 0 pic intr output 12 pic irq12 1 pic irq1 13 pic irq13 (?ating-point error) 2 pic irq0 (pit) 14 pic irq14 3 pic irq3 15 pic irq15 4 pic irq4 16 pirqa_l 5 pic irq5 17 pirqb_l 6 pic irq6 18 pirqc_l 7 pic irq7 19 pirqd_l 8 pic int8 (rtc) 20 gpio28 9 pic irq9 21 gpio29 10 pic irq10 22 gpio30 11 pic irq11 23 gpio31 46functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.4.3 watchdog timer (wdt) the watchdog timer is a down counter starting at a programmed value. it resets or shuts down the system if the count reaches zero. operating system services periodically restart the timer so that if the operating system, drivers or services stop functioning, the system is automatically restarted or shut down. the watchdog timer is enabled or disabled by programming devb:0xa8. when disabled, the watchdog timer stops counting and cannot be started by the operating system. when enabled, the watchdog timer supports two sub-states, the running and the stopped states. the watchdog timer allows the operating system to set it in either running or stopped state by programming wdt00[rstop]. in the enabled/stopped state the timer does not count down. in the enabled/running state the counter counts down to zero once triggered. these states are visible to the operating system through wdt00[wde_alias] and wdt00[rstop]. when devb:0xa8[wdtsilent] is set, the watchdog timer operates in silent mode. in that mode no action, as de?ed in wdt00[wact], is caused when the timer expires. it is in the responsibility of external software to cause either a power down/power up or a system reset and to clear wdt00[wfir] directly. the status of wdt00[wfir] can be observed externally on gpio4 when the gpio is programmed for its alternate function through pmc4. the count down time range can be programmed by writing wdt08. 3.4.4 high precision event t imer (hpet) 3.4.4.1 overview the hpet consists of a block of three timers. this block contains a 32-bit up counter with three 32- bit output comparators each for one timer. timer 0 can operate in either periodic or non-periodic mode, timer 1 and 2 only in non-periodic mode. table 17. hpet speci?ations item implementation main counter 32-bit up-counter clock frequency 14.31818 mhz number of comparators 3 32-bit comparators number of periodic capable timer 1 timer 0 number of one-shot capable timer 3 timer 0, 1, 2 interrupt routing through pic, ioapic and hypertransport link chapter 3 functional operation 47 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 4. high precision event timer block diagram 3.4.4.1.1 periodic mode only timer 0 supports the periodic mode. in the periodic mode the comparator consists of a comparator value and an accumulator register. depending on the state of hpet100[setval], a write to hpet108 is stored either to the comparator value register or to the accumulator register. if the main counter value matches the accumulator value, an interrupt is generated (if enabled) and the last value written to the comparator value register is added to the accumulator value register. in periodic mode the value of the accumulator register is given back for read accesses to hpet108. to change the comparator value register, the software should either halt the main counter or disable the comparator to avoid races. 14.31818 mhz 32 bit up counter c0 + c0 c1 c2 interrupt routing hypertransport inti[x:y] inti8 inti2 ioapic pic irq8 irq0 32 32 32 (roll over) accu link 48 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.4.4.1.2 non-periodic mode all timers support the non-periodic (one-shot) mode. the timer generates an interrupt if either the comparator value matches the main counter value or the main counter wraps around. during runtime the hardware does not change the value of the comparator value register, but the software may reprogram it. 3.4.4.1.3 interrupt routing the timer interrupts can be routed to the pic and/or the ioapic. in legacy mode (hpet10[lien] set to 1b), timer0 interrupt is routed to irq0/intin2 and timer1 interrupt to irq8/intin8 of pic/ioapic. timer2 is only routed directly to the ioapic. in non-legacy mode all three timers are routed to the ioapic. the timers can be routed to all ioapic inputs with the exception of intin0, intin2, intin8, intin13 and intin20 to intin23. chapter 3 functional operation 49 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 5. high precision event timer interrupt routing 3.4.4.2 register mapping all hpet registers are memory mapped and 64-bit aligned. the bios reports the base address location and the allocated space to the operating system. the operating system should never change the base address register. this implementation consists of a 1-kbyte address space. the base address register for these registers is devb:0xa0. software should not write to read-only registers. software must not attempt to read or write across register boundaries. that means 32-bit accesses are only allowed on 32-bit boundaries. software should perform read-modify-write on reserved bits. 3.4.4.3 power management the timer registers are not powered during s3, s4 and s5. all functions of the timer are only used during s0, and all interrupts should be disabled before leaving s0. hpet pit pic irq8 sl_irq8 irq0 lien ioapic intin2 intin8 t1irq t0irq lien t2irq t1irq t0irq t0introute[4:0] t1introute[4:0] t2introute[4:0] intin13 1 1 1 1 1 1 1 decode intin4 intin3 intin5 & & intin17 intin18 intin19 bus master intin0 note: high precision event timers can be routed only to intinx inputs 1, 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 16, 17, 18 and 19 (i.e., all except 0, 2, 8, 13 and 20 to 23). 50 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.4.5 real-time clock (logic powered by vdd_coreal) the real-time clock logic requires an external 32-khz oscillator. it includes a clock and calendar timer, an alarm which generates an interrupt, and 256 bytes of non-volatile ram. it is register compatible with the legacy pc real-time clock. it meets acpi real-time clock requirements. the real- time clock resides on the vdd_coreal power plane. 3.5 enhanced ide controller the enhanced ide controller supports independent primary and secondary ports. each port supports two drives. supported protocols include pio modes 0-4, multi-word dma modes 0-2, ultra dma modes 0-1, 2 (ata-33), 3, 4 (ata-66), 5 (ata-100), and 6 (ata-133). the ide ports can be individually controlled through devb:1x54 such that the drives can be powered down. 3.6 system management bus 2.0 controller 3.6.1 functional overview the smbus controller is designed to implement an smbus 2.0 compliant host and slave device. the smbus controller constitutes a pci function with its according pci con?uration header. host accesses to the smbus controller are accomplished through an acpi 2.0 chapter 13 compliant host interface comprising a data and a status/command port. see the acpi 2.0 speci?ation, sections 13.1?3.7 for operational details of that interface. notes: 1. the smbus controller target state machine accepts neither non-de?ed commands nor out-of- order data accesses like write accesses to the data port without a preceding write access to the command port. in those situations, the access is terminated by a master abort. 2. an out-of-order write access to the command port r e-initialize s the target state machine to that latter command. to this effect a write access to the command port starting a write command following a preceding read command t erminate s that read command and re-initialize s the target state machine to the write command. 3.6.2 interrupts see figure 6 on page 52 for the interrupt structure of the smbus controller. all interrupts can be con?ured by devb:2x48[set_scists_en, set_intsts_en] to generate an smi or sci through pm20[smbc_sts] or a pci interrupt through sc08[int_sts]. the internal interrupt sources comprise the events associated with sc04[sci_evt, obf, ibf] as described by chapter 13 of the chapter 3 functional operation 51 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information acpi 2.0 speci?ation. sc04[sci_evt] comprises three sources of events with each source having an unique noti?ation header associated with it (see table 18). if there are more than one with sc04[sci_evt] associated event pending, the noti?ation header with the highest priority is returned upon a query command from the host with priority 1 being the highest priority. table 18. sc04[sci_evt] event sources event source priority notification header smbalert 1 80h smbus host controller 2 20h 52 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information figure 6. smbus controller interrupt model note that all noti?ation headers are set by event generators, i.e., by edge sensitive sources. in the case of an smbalert detection, software is expected to query the attached smbus devices until all devices that asserted smbalert in parallel are serviced. & smbalert 80h sc08[smbalert_en] smb01[xxx] 20h done alarm status 1 1 ibf=0 obf=1 sci_evt ibf obf 1 & & & sc08[int_sts] sc08[int_en] devb:2x48[set_intsts_en] devb:2x48[set_scists_en] pci_smbc_irq set_smbc_sts sci_evt=1 noti?ation header, sticky event generator (set pulse) status bit, sticky, r/clr status bit, non-sticky, ro enable bit, r/w sc04[xxx] priority 1 priority 2 chapter 3 functional operation 53 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 3.7 system management logic system management includes logic for most of the multiplexed-function pins?uch as general- purpose i/o (gpio) pins, the power management (pm) pins, system management bus 1.0 (smbus 1.0) pins, the processor interface pins, and the plug and play (pnp) interrupt pins?s well as the logic required for acpi-compliant power management for desktop and mobile systems. programmable register access to most of this logic is contained in the devb:3xxx con?uration space and the pmxx i/o space. the major functions are: ? acpi interrupt (sci or smi based on the state of pm04[sci_en] status bits and enables ? smi status bits and enables ? system power state machine (spsm) ? resume event logic (to place the spsm into the full-on state) ? smbus 1.0 interface ? system power state control pins and general purpose pins ? device monitors (hardware traps, interrupt traps, dma request traps, re-trigger timers) ? system inactivity timer ? serial irq logic ? clkrun_l control ? watchdog timer 3.7.1 power management the following table summarizes all the system management events that can be detected by the system management logic and the hardware response enable registers. the columns are: sci/smi parent sts/en, where the status and enable bits for acpi interrupts are accessible; and smi-only sts/en, where the status and enable bits for smi interrupts are accessible. table 19. system management events events sci/smi parent sts/en smi-only sts/en notes, other functions os release (pm04[gbl_rls]) pm28/2a smi only bios release (pm2c[bios_rls]) pm00/02 sci only software smi through pm1e, pm2f pm28/2a smi only device monitors; gp timer time out pm20/22 pma0/a8 see pm[8c:50] for de?itions; child sts/en bits in pma0/a4 system inactivity timer time out pm20/22 pm20/2a see pm98 for sit; reload registers in pm[8c:50] and pmac acpi timer over?w pm00/02 sci only smbus 1.0 events pm20/22 pm28/2a child sts/en bits in pme0/e2 54 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.7.1.1 sci and smi control system management events cause corresponding sts registers to be set. sts registers can be enabled to generate sci and smi interrupts. the following diagram shows how the sts registers are routed to the interrupts. usb bus resume event pm20/22 pm20/2a ac ?7 events pm20/22 pm20/2a smbus 2.0 events pm20/22 pm20/2a power button override pm00 no sci; pm26 control only used to go to soff tco events pm20/22 pm28/2a miscellaneous smi events pm30/32 pic intr signal (unmasked irqs) reload sit through pmac; also causes c2/c3 resume; pos resume through pm28/2a real-time clock irq pm00/02 sci only nmi to processor reload sit through pmac; also causes c2/c3/pos resume init to processor reload sit through pmac; also causes c2/c3/pos resume smi to processor also causes c2/c3/pos resume pci bus masters pm00 resumes from c3 with no sci; reload sit through pmac; re-trigger timer through pm54 32 gpio inputs pmb0/b4 pmb0/b8 pwrbtn_l pin pm00/02 pm00/2a extsmi_l pin pm20/22 pm002a pme_l pin pm20/22 pm20/2a ri_l pin pm20/22 pm20/2a slpbtn_l pin pm00/02 pm00/2a therm_l pin pm20/22 pm20/2a lid pin pm20/22 pm20/2a acav pin pm20/22 pm20/2a table 19. system management events (continued) events sci/smi parent sts/en smi-only sts/en notes, other functions chapter 3 functional operation 55 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 7. sts to interrupt routing the and-or?boxes in the middle of the diagram specify the logical and of the sts and en registers (or sts and smi_en registers, as the case may be), the results of which are logically ored together; for example: (sts1 & en1) | (sts2 & en2)..., and so on. all enabled acpi interrupts may be routed to either sci or smi interrupts by pm04[sci_en]. or these sts registers may be routed directly to smi by using the smi_en registers, regardless of the state of pm04[sci_en]. the usb controllers and the serial irq logic also provide sources of smi that is ored into the logic. smi and sci are inputs to the interrupt routing logic; see section 3.4.2 on page 40. 3.7.1.2 device monitors and re-trigger timers device monitors consist of a set of registers that may be used to enable traps on transactions, interrupts, dma activity, and device inactivity. each monitor circuit includes transaction decode logic, optional interrupt and dma channel enables, a re-trigger timer that gets reloaded every time the monitored event occurs, and enable bits for passing events to sci or smi interrupts. interrupt device monitor events occur whenever the monitored interrupt signal changes state (high to low or low to high). dma device monitor events occur whenever the monitored dma request signal (to the legacy 8237 dma controller from the lpc interface logic) is asserted. sts register en register and- or and- or and- or acpi or usb keyboard emulation interrupt and smi pm04[sci_en] 1 0 pm2c[smi_en] sci acpi or or serial irq smi output and- or and- or and- or and- or and- or sts register en register sts register en register smi_en register sts register en register smi_en register sts register en register smi_en register pm00 events device monitors pm[8c:40] pm20 events smbus events gpio pins pm[df:c0] 56functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information figure 8. device monitors and retrigger timers 3.7.1.2.1 traps con?uration registers devb:3x[d8:b4] specify several traps for memory, i/o, and con?uration space address ranges. these traps are generated for the speci?d transactions that (1) are targeted at the ic or any device on or behind the secondary pci bus or any devices on the lpc bus, (2) are not targeted to the con?uration space or i/o space of the ide controller, and (3) are not targeted at any of the deva:0x[ff:c0] con?uration registers. 3.7.1.3 system inactivity timer any of the hardware traps, irq lines, or pci bus master activity can be enabled to reload the system inactivity timer (sit). if the sit decrements to zero, then, if enabled, an interrupt is generated. 3.7.1.4 throttling logic when throttling, the ic repetitively places the processor into the stop grant state for a speci?d percentage of time in order to reduce the power being consumed by the processor. stpclk_l is used to control the processor stop grant state with a period speci?d by devb:3x40[ntper, ttper] and a duty cycle speci?d by devb:3x40[thminen], devb:3x4d and pm10. two types of throttling are possible: normal and thermal. normal throttling is controlled by software. thermal throttling is controlled by the therm_l pin (see also devb:3x40[th2sd]). if both are triggered active simultaneously, then the duty cycle speci?d for thermal throttling is used. throttling is only possible when in the fon state. if throttling is enabled when entering other states, then it stops; after exiting the state, throttling resumes. 3.7.1.5 clkrun_l pci bus clock control pci bus clock control is performed with the clkrun_l signal and associated protocol as de?ed by the pci mobile design guide. the ic is the ?entral resource with regard to clkrun_l protocol. 3.7.1.5.1 enabling pci clkrun_l protocol clkrun_l protocol is enabled by pmc5. clkrun_l assertion by an external device is ignored during the s1 sleep state. reload retrigger timer re-trigger timer time out or or sts bit in pma0 interrupt select dma request select address decode chapter 3 functional operation 57 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 3.7.1.5.2 pcistop_l assertion the pclk input to the ic is required to always operate regardless of the clkrun_l protocol. the pci clock to external devices is stopped when the ic asserts pcistop_l. if the pci bus has been idle for 26 pci clocks (internally and externally) and there is no host access to or bus master request from any device in the ic other than ide, the ic deasserts clkrun_l by driving it high for one pci clock period and then three-stating it. if the ic does not sample clkrun_l asserted by an external device within 3 pci clock periods of clkrun_l deassertion, then the ic asserts pcistop_l. 3.7.1.5.3 pcistop_l prevention if the ic has detected an idle condition as speci?d in the previous section and has deasserted clkrun_l, an external device may keep the external pci clock running by asserting clkrun_l within 2 clocks of clkrun_l deassertion. if the ic detects clkrun_l asserted within 3 clocks of deasserting clkrun_l, then the ic reasserts clkrun_l, clears its 26 clock idle counter and does not assert pcistop_l. if the ic has deasserted clkrun_l and detects any host access to or bus master request from any device in the ic other than ide or an acpi system state transition within 3 pci clocks of deasserting clkrun_l, then the ic reasserts clkrun_l, clears its 26 clock idle counter and does not assert pcistop_l. 3.7.1.5.4 pcistop_l deassertion the ic deasserts pcistop_l under the following conditions: ? it detects clkrun_l asserted by an external device. ? it detects any host access to or bus master request from any device in the ic other than ide. ? it detects a resume event from s1. ? it asserts reset_l. the ic restarts the pci clock to external devices by deasserting pcistop_l. the ic asserts clkrun_l when it deasserts pcistop_l. the clkrun_l pin requires a large (100-kohm or greater) external pull-up resistor to the vdd_io plane. 3.7.1.6 system power state controller (spsc) the system power state controller (spsc) supports the following system power states: 58 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information mechanical off (moff or acpi g3 state). moff is the state when only vdd_rtc is powered. this can happen at any time, from any state, due to the loss of power to the aux planes (e.g., a power outage, the power supply is unplugged, or the power supply s mechanical switch). when power is applied to aux, then the system transitions to either fon or soff. soft off (soff or acpi g2/s5 states). in the soff state, the system appears to the user to be off. the aux planes of the ic are powered, but the main supplies are not; rpwron is low to disable power system dram. the system normally uses pwrbtn_l to transition from soff to fon. table 21 on page 59 lists all resume events that may cause a transition from soff to fon. suspend to disk (std or acpi s4 state). the ic s behavior in this state equivalent to soff. suspend to ram (str or acpi s3 state). in the str state, the system s context is stored in system memory (which remains powered; rpwron is high) and the main power supplies are shut off (pwron_l high). the behavior of the ic in the str state is similar to soff; the main difference is that rpwron is asserted in str. power on suspend (pos or acpi s1 state). all power planes to the ic are valid in pos. signal control during pos is speci?d by devb:3x50. table 21 on page 59 lists all resume events that may cause a transition from pos to fon. stop grant caches snoopable (c2). in c2, the processor is placed into the stop grant state. signal control during c2 is speci?d by devb:3x4f. it is expected that the processor s cache may be snooped while in this state. table 21 on page 59 lists all resume events that may cause a transition from c2 to fon. stop grant caches not snoopable (c3). in c3, the processor is placed into the stop grant state such that the processor s cache cannot be snooped; requests that result in snoops are resume events (see pm04[bm_rld]). signal control during c3 is speci?d by devb:3x4f. table 21 on page 59 lists all resume events that may cause a transition from c3 to fon. full on (fon or acpi s0). in fon, all the power planes are powered and the processor is not in the stop grant state. figure 9 shows the system power state transitions. table 20. system power states system power state vdd_io, vdd_core vdd_iox, vdd_corex vdd_rtc full on (fon; s0) on on on c2 on on on c3 on on on power on suspend (pos; s1) on on on suspend to ram (str; s3) off on on soft off (soff; s5); suspend to disk (std; s4) off on on mechanical off (moff; g3) off off on chapter 3 functional operation 59 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 9. system power state transitions 3.7.1.6.1 summary of resume events in general, resume events occur when there is an event that sets a status bit while the acpi interrupt enable for that status bit is active. if ldtstop_l is asserted in the low-power state, then resume events do not initiate the resume sequence until the minimum assertion time of 1 microsecond for ldtstop_l has completed. table 21. resume events resume event resumes from sleep states resume event enable pwrbtn_l s5-s1, c3/c2 n/a slpbtn_l s5-s1, c3/c2 pm02[slpbtn_en] rtc alarm s5-s1, c3/c2 pm02[rtc_en] ri_l s5-s1, c3/c2 pm22[ri_en] pme_l s5-s1, c3/c2 pm22[pme_en] ethernet controller pme s5-s1, c3/c2 pm22[pme_en], ethernet controller pm registers acav s5-s1, c3/c2 pm22[acav_en] lid s5-s1, c3/c2 pm22[lid_en] smbus 1.0 events s5-s1, c3/c2 pm22[smbus_en] smbalert0_l s1, c3/c2 pm22[smbus_en], pme0[smba_sts] usb events s5-s1, c3/c2 pm22[usbrsm_en] str(s3) suspend to ram pwron_l high rpwron high soff(s5)/std(s4) soft off/suspend to disk pwron_l high rpwron low moff(g3) mechanical off c2 stop grant c3 stop grant caches not snoopable see devb:3x4f pos(s1) clock-control based fon(s0) full on pwron_l , rpwron asserted caches snoopable power reduction and sleep state see devb:3x50 resume event cpu initiated (pm04) resume event cpu initiated (pm04) resume event cpu initiated (pm04) resume event cpu initiated (pm04) resume event cpu initiated (pm04) power vdd_aux power failure devb:3x43[g3tos5]==0 or devb:3x43[vdda_sts]==1 applied and vdd_aux power applied, devb:3x43[g3tos5]=1, and devb:3x43[vdda_sts] = 0 60 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information pm26[batlow_ctl] can be used to inhibit resume events in s5-s1. 3.7.1.6.2 transitions between moff/soff/std/str and fon in the following timing diagrams, rtc cycles refer to 32 khz clocks cycles. extsmi_l s5-s1, c3/c2 pm22[extsmi_en] smbus 2.0 events s5-s1, c3/c2 pm22[smbc_en] smbalert1_l s5-s1, c3/c2 pm22[smbc_en], sc08[smbalert_en] ac ?7 events s5-s1, c3/c2 pm22[ac97_en] gpio[25, 24, 23, 22, 18, 14, 3, 2, 1, 0] s5-s1, c3/c2 pmb4[25, 24, 23, 22, 18, 14, 3, 2, 1, 0] therm_l s1, c3/c2 pm22[therm_en] tco sci s1, c3/c2 pm22[tcosci_en] system inactivity timer s1, c3/c2 pm22[sit_en] device monitor events s1, c3/c2 pm22[dm_en] device monitor events s1, c3/c2 pma4 gpio[31:26, 21:19, 17:15, 13:4] s1, c3/c2 pmb4[31:26, 21:19, 17:15, 13:4] unmasked interrupt s1, c3/c2 pm2a[irq_rsm] for s1, n/a for c3/c2 nmi, init, smi c3/c2 n/a bus master request c3 pm04[bm_rld] table 21. resume events (continued) resume event resumes from sleep states resume event enable chapter 3 functional operation 61 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 10. transitions from moff to soff and from soff/std/str to fon reset_l. ldtrst_l dcstop_l suspend_l agpstop_l ldtstop_l pwron_l rpwron pwrok resume event vdd_io, vdd_core rst_soft vdd_iox, vdd_corex 25 to 50 msec see note1 1 to 2 rtc cycles more than 50 msec 1 to 2 rtc cycles 1 sec 1.5 to 2.0 msec (see note 5) (see note 6) (see note 2) moff to soff soff/std/str to fon notes: 1 . if devb:3x43[g3tos5] = 0, then the time from the end of rst_soft to pwron_lassertion is 1 to 2 rtc clocks. if devb:3x43[g3tos5] = 1, then the resume event must occur before pwron_l is asserted. 2 . rpwron is high during str and low during std and soff. 3 . ldtstop_l powers up deasserted simultaneously with the vdd_io power plane. 4 . vdd_io is representative of all main power planes. vdd_iox is representative of all aux power planes. 5 . when transitioning from str to fon, suspend_lis not deasserted until one microsecond after reset_lhas been deasserted. 6 . when transitioning from soff/std/str to fon, agpstop_ldeassertion is delayed from dcstop_l deassertion by 500us to 800us. (see note 3) 62 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information figure 11. transitions from fon to soff/std/str 3.7.1.6.3 transitions from any state to g3 (moff) transitions from any state to g3 (moff) occur whenever there is a power failure. no speci? sequence is ensured when a power failure occurs. however the ic isolates its al power plane from all other power planes when a transition to g3 occurs. 3.7.1.6.4 transitions from s0/c0 (fon) to c2/c3 devb:3x4f speci?s the enabled functions for transitions to c2 and c3. the sequence of entering c2/c3 is as follows: ? processor initiation. software initiates the transition to c2 by reading pm14 or to c3 by reading pm15. ? stop-grant. ic issues a hypertransport stpclk system management message with the 3-bit system management action field (smaf) as de?ned by devb:3x70[c2smaf] for c2 or devb:3x70[c3smaf] for c3. this stpclk system management message is issued before the stpclk message stop grant message agpstop_l dcstop_l suspend_l ldtstop_l reset_l, ldtrst_l pwron_l rpwron pwrok vdd_io, vdd_core 1 to 2 rtc 4 rtc 1 rtc 1 rtc 1 rtc (see note 4) for s3 for s4/s5 notes: 1. for transitions to soff that are initiated by a power/sleep button override event, or thermtrip_lassertion, or portcf9[fullrst], the stpclk_l assertion and stop grant cycles are skipped; the sequence starts with the assertion of agpstop_l. 2. stpclk is transmitted by a hypertransport system management message with the 3-bit system management action field (smaf) as de?ned by devb:3x70[strsmaf] or devb:3x70[s45smaf]. this stpclk system management message is issued before the response message to the write of pm04 is issued. 3. reset_l is asserted within 1200ns of thermtrip_l assertion. 4. these signals go unde?ned when power is removed. (see note 3) chapter 3 functional operation 63 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information response message to the read of pm14 or pm15. the ic then waits for a stop grant special cycle broadcast message from the host. when the ic receives the broadcast stop grant message, the transition to c2 is complete; the remaining steps only apply to the transition to c3. ? agpstop_l. if devb:3x4f[astp_c3en]=1b, the ic asserts agpstop_l when it recognizes the stop grant special cycle associated with the c3 state. ? cpusleep_l. if devb:3x4f[cslp_c3en]=1b, the ic asserts cpusleep_l when it recognizes the stop grant special cycle associated with the c3 state. ? ldtstop_l. after the stop grant special cycle is recognized, the ic waits the time interval dictated by devb:3x74[c3s1lst], then if devb:3x70[c3ls]=1b the ic asserts ldtstop_l. 3.7.1.6.5 transitions from c2 to c0 (fon) when the ic detects an enabled resume event, it issues a hypertransport stpclk system management message with the stpclk bit deasserted. 3.7.1.6.6 transitions from c3 to c0 (fon) the following is the resume sequence from c3, once an enabled resume event occurs. note: if cpusleep_l is not enabled to be asserted in c3 by devb:3x4f, then the c3 resume sequence starts from ?dtstop_l?below: ? cpusleep_l. if devb:3x4f[cslp_c3en]=1b then, when an enabled resume event occurs, cpusleep_l is deasserted and a 250 s delay is inserted before the rest of the c3 resume sequence occurs. if devb:3x4f[cslp_c3en]=0b then cpusleep_l is not part of the c3 sequence, and the 250 s delay is not inserted between recognizing an enabled resume event, and deassertion of ldtstop_l. ? ldtstop_l. if devb:3x70[c3ls]=1b then ldtstop_l is deasserted when the ic detects an enabled resume event (unless cpusleep_l was asserted). see devb:3x74[fvlst]. ? agpstop_l. if cpusleep_l is used and ldtstop_l is not used then agpstop_l is deasserted 250 s after cpusleep_l deassertion (as mentioned above). if ldtstop_l is used then after ldtstop_l deassertion a delay dictated by devb:3x52[c3_astp_dt] occurs before agpstop_l is deasserted. if ldtstop_l and cpusleep_l are not used then after a programmable time period dictated by devb:3x52[c3_astp_dt] after the resume event agpstop_l is deasserted. ? after ldtstop_l and agpstop_l are deasserted, the ic issues a hypertransport stpclk system management message with the stpclk bit deasserted. 3.7.1.6.7 transitions from fon (s0/c0) to pos (s1) devb:3x50 speci?s the enabled functions for transitions to s1. the transition to s1 occurs as follows for each of the enabled pin controls: ? processor initiation. software initiates the transition to s1 by writing the appropriate value to pm04[slp_typ, slp_en]. 64 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information ? stop-grant. ic issues a hypertransport stpclk system management message with the 3-bit system management action field (smaf) as de?ned by devb:3x70[possmaf]. this stpclk system management message is issued before the response message to the write of pm04. the ic then waits for a stop grant special cycle broadcast message from the host. ? cpusleep_l and cpustop_l . if devb:3x50[cslp]=1b, devb:3x50[cstp]=1b, then cpusleep_l, cpustop_l respectively are asserted when the ic recognizes stop grant special cycle broadcast. ? agpstop_l. if devb:3x50[astp]=1b then agpstop_l is asserted immediately after the stop grant broadcast has been recognized by the ic. ? dcstop_l. if devb:3x50[dcstp]=1b the ic waits a minimum of 122 s after stop grant is recognized and then asserts dcstop_l. ? suspend_l. if devb:3x50[susp]=1b suspend_l is asserted at the same time that dcstop_l is asserted. if dcstop_l is not enabled suspend_l assertion is delayed a minimum of 122 s from stop grant. ? pcistop_l. if devb:3x50[pstp]=1b after dcstop_l or suspend_l assertion (or stop grant if neither are enabled) the ic then waits at least one rtc clock before asserting pcistop_l. pci clkrun_l protocol is not in effect during s1. ? ldtstop_l. after dcstop_l or suspend_l or pcistop_l (if enabled) is asserted, the ic waits the time interval dictated by devb:3x74[c3s1lst] then, if devb:3x70[posls]=1b, the ic asserts ldtstop_l. 3.7.1.6.8 transitions from s1 (pos) to s0 (fon) the following is the s1 resume sequence, once an enabled resume event occurs: ? pcistop_l, cpusleep_l, cpustop_l. if these signals are asserted, then they are deasserted immediately after an enabled resume event is detected. ? ldtstop_l. ldtstop_l is deasserted immediately after an enabled resume event is detected. see devb:3x74[fvlst]. ? dcstop_l, suspend_l. the ic waits a programmable amount of time dictated by devb:3x54[pllcnt1] after ldtstop_l is deasserted and then deasserts dcstop_l and suspend_l. if ldtstop_l is not asserted during s1 then the delay is from the detected resume event. ? agpstop_l. the ic waits a programmable amount of time dictated by devb:3x54[pllcnt] after dcstop_l or suspend_l or ldtstop_l deassertion (if dcstop_l or suspend_l is not used) and then deasserts agpstop_l. ? after the ic has deasserted agpstop_l, it issues a hypertransport stpclk system management message with the stpclk bit deasserted. chapter 3 functional operation 65 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 3.7.2 serial irq protocol the ic supports the serial irq protocol. this logic controls the serirq pin and outputs irqs to the pic and ioapic blocks. this logic runs off of pclk. it is speci?d by devb:3x4a. the serial irq logic does not provide support for generating irq0, irq2, irq8, or irq13. in order to use irq[15, 14, 12, 6, or 1], the corresponding external irq pin must be pulled high. the pci irqs from the serial irq logic are routed to the interrupts speci?d by devb:3x56. 3.7.3 smbus 1.0 the ic includes a system management bus 1.0, or smbus 1.0, interface. smbus is a two-wire serial interface typically used to communicate with system devices such as temperature sensors, clock chips, and batteries. the control registers for this bus are pme0 through pmef. the smbus interface includes a host controller and a host-as-slave controller. host controller. the host controller is used to generate cycles over the smbus as a master. software accomplishes this by setting up pme2[cyctype] to specify the type of smbus cycle desired and then (or concurrently) writing a 1 to pme2[hostst]. this triggers an smbus cycle with the address, command, and data ?lds as speci?d by the registers called out in pme2[cyctype]. writes to the host controller registers pme2[3:0], pme4, pme8, and pme9 are illegal while the host is busy with a cycle. if a write occurs to pme2 while pme0[hst_bsy] is active, then the four lsbs are ignored. writes to pme4, pme8, and pme9 while pme0[hst_bsy] is active are ignored (the transaction is completed, but no data is transferred to the smbus controller). if an smbus-de?ed time out occurs while the host is master of the smbus, then the host logic attempts to generate a smbus stop event to clear the cycle and pme0[to_sts] is set. the host controller is only available in the fon state. host-as-slave controller. the host-as-slave controller responds to word-write accesses to either the host address speci?d by pmee or the snoop address speci?d by pmef. in either case, if the address matches, then the subsequent data is placed in pmec and pmea. in the case of snoop accesses, the command information is stored in pmec[7:0] and the data is stored in pmea[15:0]. in the case of addresses that match the pmee host-as-slave address register, then the address is stored in pmec[7:1]?f the transaction includes a 7-bit address?r pmec[15:1]?f the transaction includes a 10-bit address. after the address match is detected, the logic waits for the subsequent stop command before setting the appropriate status bits in pme0[hslv_sts, snp_sts]; however, if a time out occurs during the cycle, after the address match is detected, then the appropriate bits in pme0[hslv_sts, snp_sts] are set. if one of the slave status bits, pme0[hslv_sts, snp_sts], is set and another access to the host slave controller is initiated, then it is not acknowledged by the ?st smbus acknowledge cycle until the status bit is cleared. the host-as-slave controller operates in all system power states except moff; it can be used to generate interrupts and resume events. 66 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information smbalert. the host controller includes support for the smbalert_l signal. if this signal is asserted, then it is expected that software determines the source by generating a host read cycle to the alert response address, 0001100b. if the smbus host controller detects this address for a read cycle with pme2[cyctype] set to receive byte (001b), then it stores the address returned by the smbalert_l slave in pme6[7:0]. if bits[7:1] of this address are 1111_0xxb, indicating a 10-bit address, then it stores the next byte from the slave in pme6[15:8]. 3.7.4 plug and play irqs the ic supports three pnp irqs. the register that speci?s these is devb:3x44. the pnpirq[2:0] pins are multiplexed with gpio functions; the control registers that specify the functions (pmd3, pmd4, and pmd5) must be set up appropriately for the pnp functions to operate. 3.7.5 general purpose i/o the general-purpose i/o pins, gpio[31:0], can be assigned to be inputs, outputs, interrupt generators, or bus controls. these pins can be programmed to be general-purpose i/o or to serve alternate functions; see the pm[df:c0] register de?itions. most of these pins are named after their alternate functions. there is one control register for each pin, pm[df:c0]. irq status and enables are available for each pin in registers pmb0 and pmb4; smi enables are available in pmb8. general-purpose i/o functions. when programmed as a gpio pin, the following functions are available: ? outputs C can be set high or low. C can be controlled by gpio output clocks 0 or 1 (see pmbc). ? inputs C active high or active low programmable. C sci or smi irq capable. C can be latched or not latched. C inputs can be debounce protected. the following diagram shows the format for all gpio pins. the input path is not disabled when the output path is enabled or when the pin is used for an alternate function. chapter 3 functional operation 67 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 12. gpio pin format debounce. the input signal must be active and stable for 12 to 16 ms before the output signal will be asserted. gpio output clocks. there are two gpio output clocks numbered 0 and 1. their behavior is speci?d by pmbc. each output clock includes a 7-bit programmable high time, a 7-bit programmable low time, and the counter can be clocked by one of four frequencies. here are the options: the output of the two gpio output clocks can be selected to drive the output of any of the gpio pins. they may be used to blink leds or for other functions. 3.8 ac '97 controller 3.8.1 introduction the ac ?7 host controller implementation supports the following features: independent pci functions for audio (function 5, address space devb:5xxx) and modem (function 6, address space devb:6xxx) independent channels for pcm in, pcm out, microphone in, modem in, modem out table 22. gpio output clock options pmbc[clk[1,0]base] base clock period output high time range output low time range 00b 250 s 250 s to 32 ms 250 s to 32 ms 01b 2 ms 2 ms to 256 ms 2 ms to 256 ms 10b 16 ms 16 ms to 2 s 16 ms to 2 s 11b 128 ms 128 ms to 16.4 s 128 ms to 16.4 s ff ltch_sts latch to interrupt generator or alternative logic 1 0 latch q d le debounce circuit 1 0 1 0 1 0 gpio output clocks 0 and 1 output mode pad 68 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 2-channel stereo for pcm audio in, 2-, 4-, 6-channel stereo for pcm audio out 16 bit sample resolution multiple sampling rates up to two codecs an ac '97 sub-system includes a digital controller and a set of up to two codecs referred to as audio codec (ac) and modem codec (mc). the codecs are in one or two physically separate chips, and are connected to the digital controller through an ac-link serial interface. the ac ?7 controller does not distinguish between primary and secondary codec. since registers do distinguish between acsdi0 and acsdi1 for reporting wake events, codec status etc. the ac ?7 controller documentation assumes the primary codec being attached to acsdi0 and the secondary codec being attached to acsdi1. supported codec con?urations are: ac as primary mc as primary ac as primary and mc as secondary ? ac as primary and ac as secondary amc as primary the ic does not support optional test modes as outlined in the ac ?7 speci?ation. figure 13. a c ?7 codec connections ac ?7 controller acrst_l acsdo acsdi0 acsdi1 acclk acsync primary codec secondary codec chapter 3 functional operation 69 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information see the ac '97 speci?ation for further information. 3.8.2 ac ?7 serial link interfac e the ac ?7 serial link interface is designed to be ac '97 revision 2.2 compliant. for a detailed description of the ac-link interface see the ac '97 speci?ation. the ic supports up to two acsdi signals for use with a primary and secondary codec. depending on which codec (ac, mc, amc) is attached, various input slots might be valid or invalid. with the exception of the input tag slot 0 those input slots must be completely orthogonal, i.e., no two data slots at the same location are valid on both input signals. this precludes the use of two similar codecs (e.g., two acs or mcs) that use the same data slots. the codec ready bit 15 of input slot 0 indicates whether the codec on the ac-link is ready for normal operation. the codec ready bits from the input slots 0 at acsdi0 and acsdi1 are visible through the global status controller register. software must further probe the powerdown control/status register in the codec to determine exactly which subsections, if any, are ready. the output slot 1 provides a command port to control features and monitor status of an ac ?7 codec. the control interface architecture supports read/write accesses to a maximum of 64 16 bit codec registers, addressable on even byte boundaries. only the even register addresses are valid. the input slot 1 tag bit in input slot 0 only pertains to the control register index data from a previous read. slot request bits are always valid and thus have to be checked independent of the slot 1 tag bit. the ic does implement transmission of gpio values to the codec in output slot 12. the values of the bits in this slot are the values written to the gpio pin status codec register at 54h/d4h. the following rules govern the usage of slot 12. ? slot 12 is marked invalid by default on coming out of reset and remains i nvalid until a gpio pin status codec register write. ? a gpio pin status codec register write causes t he write data to be transmitted in slot 12 in the next possible frame, with slot 12 marked valid, and the address/data information to be transmitted in slots 1 and 2 of the same frame. ? after the ?st gpio pin status codec register write, slot 12 remains valid for all following frames. the data transmitted in slot 12 is the data last written to the gpio pin status codec register. any subsequent write to the register causes t he new data to be sent out in the next frame. slot 12 gets invalidated after the following events: sm reset, ac ?7 cold reset, warm reset, and hence a wake-up from s3/s4/s5. slot 12 remains invalid until the next gpio pin status codec register write. the content of the gpio pin status codec register is to be returned in slot 12 of every input frame. reads from gpio pin status codec register at 54h/d4h are not transmitted across the link in slots 1 and 2. the data from the most recent slot 12 is stored in a controller shadow register and is returned. that data is also accessible in the mc48 ac ?7 controller register. 70 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information when accessing the codec registers, only one i/o cycle can be pending across the ac-link at any time. the ic internal architecture and ac ?7 controller implementation provides arbitration logic to ensure that. for compatibility reasons the cas bit in the codec access semaphore register is provided. software is to monitor the cas bit that indicates that a codec access is pending. the cas bit is set by reads from software and reset upon completion of the codec register access cycle. once the cas bit is cleared, another codec access can be initiated. the exception to this being reads to the gpio pin status codec register that are returned immediately with the most recently received input slot 12 data shadowed in a controller internal register. a read access to the gpio pin status register does not reset the cas bit upon completion while a write access to the gpio pin status register does reset the cas bit upon completion. the controller does not issue back to back reads. it must get a response to the ?st read before issuing a second. in addition, codec reads and writes are only executed once across the link and are not repeated. 3.8.3 a c '97 pci interface and bus master controlle r the ac ?7 controller is a pci bus master with scatter/gather support. the pci interface has the following characteristics: ? on reads from a codec, the controller expects t he codec to respond within the next frame, after which, if no response is received, it returns a dummy read completion to the processor (with ffh on the data) and also set s the read completion status bit in the global status register. if acclk is not operating adequately the same responses occurs i mmediately (with ffh on the data, and ac30/mc40[rcstat] set). codec register reads by the host might c ause a pci retry cycle. ? on writes to a codec, the controller returns a write completion to the processor when the write data is inserted in a frame to the codec. if acclk is not operating adequately the same response occurs i mmediately. fifo buffers are ?led and emptied in one pci transaction using double-word transfers where possible, and word transfers where necessary. data sets can be word-aligned. when host memory buffer page boundaries are crossed (i.e., need to switch to the next buffer page) more than one pci transactions are used. ? audio and modem interrupts generated by the ac '97 controller are connected to one pci interrupt request. table 23 lists the pci interrupt sources . table 23. pci interrupt sources interrupt register bit enable register bit interrupt acx6/mcx6[bcis] acxb/mcxb[ioce] scatter/gather host memory buffer completion interrupt status (i.e., buffer full/empty) acx6/mcx6[fifoerr] acxb/mcxb[feie] fifo over-run (modem in buffer) or under-run (modem out buffer) error acx6/mcx6[lvbci] acxb/mcxb[lvbcien] last valid buffer completion interrupt chapter 3 functional operation 71 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the principal function of scatter/gather (i.e., basically a memory paging mechanism) is to assist the host operating system in managing memory fragmentation. one logical buffer is split among multiple physical blocks or pages of host memory. a logical buffer is mapped to physical host memory pages using a descriptor table. the descriptor table is pointed to by the buffer descriptor list base address register. each descriptor table entry contains the physical memory address of a host memory page, the length of the page, and other information. descriptor tables have 32 entries, and are set up by a software driver. host memory page sizes of up to 64k samples are supported. the descriptor format is shown in table 24. the current descriptor in use is referenced by the current index value civ. this value basically follows the last valid index lvi by being incremented after ?ling the associated host memory buffer. the value rolls over from index 31 to index 0. so, to allow a roll-over, the descriptor table has to be set up with 32 valid entries. no roll-over from an index less than 31 can be negotiated. other than that the civ value can only be set to index 0 by applying reset to the ac ?7 controller. after reset, the ?st descriptor at index 0 is prefetched by piv. after handing over the prefetched descriptor index to civ, the next descriptor in the descriptor table is prefetched at an index incremented by one (with rolling over after index 31). also, in the case when civ equals lvi, the next descriptor is prefetched, but only processed after lvi has been incremented by software, thus providing that descriptor to the controller. this bus master logic, once set up by a software driver, automatically fetches descriptors, transfers data to and from host memory, generates interrupts, etc. as part of its implemented control mechanism. this scatter/gather control mechanism is implemented for each data stream. ac30/mc40 [srint] ac2c/mc3c [srien] secondary resume interrupt ac30/mc40 [print] ac2c/mc3c [prien] primary resume interrupt ac30/mc40 [gpiint] ac2c/mc3c [gpiien] gpi interrupt table 24. descriptor format bit description 63 ioc. interrupt on completion. when set, indicates that an interrupt should be generated upon completion of data transfer to/from the block/buffer. 62 bup. buffer underrun policy. when set to 1b the controller transmits zeros in the case that this buffer is completed and the last valid buffer has been processed. otherwise the controller transmits the last valid sample. this bit typically is set only if this is the last buffer in the current stream. 61:48 reserved 47:32 length. length of host physical memory block/buffer in words (i.e., number of 16 bit locations). 31:1 base_addr. base address of host physical memory block/buffer. 0 reserved table 23. pci interrupt sources (continued) interrupt register bit enable register bit interrupt 72 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.8.4 a c '97 data buffering data buffering inside the digital controller is provided with fifo buffers. the following buffers are provided as separate, independent buffers: audio pcm left out audio pcm right out audio pcm center front out audio pcm left rear out audio pcm right rear out audio subwoofer out audio pcm left in audio pcm right in audio microphone in modem in modem out note that the audio pcm out streams are considered one data channel and have one associated scatter/gather bus master controller (i.e., the pcm out channel). the same is true for audio pcm left in and audio pcm right in (i.e., the pcm in channel). the samples are transferred in the following order: for a given 2-, 4-, or 6-channel audio stream the audio bus master controller expects each sample compound to start with the left-front sample at the least signi?ant word address proceeded by the following samples at incremented word addresses. for a 4-channel audio stream that leads to the following sample address scheme: base_addr+0h left-front sample 0 base_addr+2h right-front sample 0 base_addr+4h left-rear sample 0 base_addr+6h right-rear sample 0 base_addr+8h left-front sample 1 table 25. pcm audio sample order audio channel ac ?7 timeslot 2-channel sample order 4-channel sample order 6-channel sample order left-front 3 1 1 1 right-front 4 2 2 2 center-front 6 3 left-rear 7 3 5 right-rear 8 4 6 subwoofer 9 4 chapter 3 functional operation 73 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information base_addr+ah right-front sample 1 ... the sample pairs left-front/right-front, center-front/subwoofer and left-rear/right-rear can be swapped by programming devb:5x4c. each fifo has the following characteristics: contains eight 16 bit samples. ? either one 16 bit word (i.e., one sample at a time) or one 32 bit doubleword (i.e., two samples at a time) can be read or written each clock using t he pci bus. transfers to/from the ac-link interface controller are done one sample a frame. the 16 bit samples are transferred as the 16 most signi?ant bits of each 20 bit slot, with the low order bits discarded for input data and padded with zeros for output data. for output buffers (to codec), ?ling is initiated by completion of passing the one-fourth empty threshold (i.e., 2 entries are empty, 6 are still full). for input buffers (from codec), emptying is initiated by completion of passing the one-fourth full threshold (i.e., 2 entries are full, 6 are still empty). for a given 2-, 4-, or 6-channel audio con?uration two principal transfer modes are supported: full rate transfer mode half rate transfer mode in full rate transfer mode all samples for the given audio con?uration are transferred in one frame. in half rate transfer mode the left front, center front, left rear samples are transferred in one frame and the right front, right rear, subwoofer samples are transferred in the following frame. see figure 14 and figure 15 on page 74 for examples of half rate transfer mode transmissions. when mono audio sample streams are transferred, software and codec must ensure both left and right samples are transferring the same data, i.e., for each mono sample two samples are transferred. the transfer modes are controlled for audio-in samples by the respective valid bits in slot 0 of the input frame and for audio-out samples by the respective request bits in slot 1 of the input frame. for audio-out samples a slot 3 request bit set to 0b causes the controller to read all audio samples for a given audio con?uration from the audio-out fifos for subsequent transmission as enabled by the request bits. for audio-in samples a slot 4 valid bit set to 1b causes the controller to write received audio samples into the audio-in fifos. the codec has to send the appropriate valid and request bits in the correct order as required by the transfer modes. repeating valid or request bits in subsequent frames out of order causes loss of data. for the example in figure 14 the slot 3, 6, and 7 request bits were set to 0b in input frame n-1 with the slot 3 request bit causing the controller to read audio samples from all audio-out fifos. according to those request bits, slot 3, 6, and 7 samples are transferred in output frame n. the slot 4, 8, and 9 request bits active (low) in input frame n cause the controller to send the already read slot 4, 8, and 9 samples in output frame n+1. the slot 3 request bit active (low) in input frame n+1 causes the controller to read new audio samples from all audio-out fifos. 74 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information output slots which are not in use for a given con?uration are always stuffed with zeros by the ic. figure 14. output frame with audio samples in half rate transfer mode figure 15. input frame with audio samples in half rate transfer mode 3.8.5 ac '97 power management logi c see the ac '97 speci?ation for a de?ition of the wake-up event protocol. ac30/mc40[print] or ac30/mc40[srint] is set when a wake-up event occurred on the ac-link and the ac ?7 controller is not in sleep state. ac2c/mc3c[prien] and ac2c/mc3c[srien] enable an ac-link wake-up event to initiate the respective ac ?7 controller interrupt. pm20[ac97_sts] is set when a wake-up event occurred on the ac-link and the ac ?7 controller is in sleep state. pm22[ac97_en] enables an ac-link wake-up event to initiate a sci or smi for the system to wake up. pm2a[ac97_en] enables an ac-link wake-up event to initiate a smi for the system to wake up. ac2c/mc3c[shutoff] can be used to disable the ac-link i/o signals. when disabled, all outputs, inclusive acrst_l, are forced low and all inputs are ignored, except for wake-up event detection. once the codec has been instructed to halt acclk, a special wake-up protocol must be used to bring the ac-link to the active mode. three methods for waking up the ac-link are supported: external wake-up warm reset cold reset slot number 0 1 2 3 4 5 6 7 8 9 10 11 12 frame n tag cmd addr cmd data x x x gpio frame n+1 tag cmd addr cmd data x x x gpio frame n+2 tag cmd addr cmd data x x x gpio slot number 0 1 2 3 4 5 6 7 8 9 10 11 12 frame n tag cmd addr cmd data x gpio frame n+1 tag cmd addr cmd data x gpio frame n+2 tag cmd addr cmd data x gpio chapter 3 functional operation 75 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information a transition from low to high at acsdi0 or acsdi1 causes the ac ?7 controller to sequence through a wake-up event detection and to ?ally report this wake-up event in pm20[ac97_sts], ac2c/mc3c[print] or ac2c/mc3c[srint], respectively, depending on the ac ?7 controllers s system state and on what acsdi[1:0] signal the event occurred. if enabled, a corresponding interrupt is issued. software then has to issue a warm or cold reset to the codec by setting the appropriate bit in the global control register to ?ish the wake-up sequence. a cold reset drives acrst_l low for a minimum of 1 s. it initializes all codec registers to their default power on reset values. internal ac-link control registers and fifos in the ac ?7 are initialized as well. the bus master control registers of the ac ?7 are not affected. a warm reset re-activates the ac-link without altering the current codec register values. it is signaled by driving acsync high for a minimum of 1 s in the absence of acclk. the ac ?7 controller is not initialized but potentially remaining slot requests from the last frame before power-down are discarded. once powered down, activation of the ac-link by re-assertion of the acsync signal must not occur for a minimum of 4 frame times following the frame in which the power down was triggered. the ac ?7 controller samples acsdi[1:0] but delay any wake-up event reporting after the above time frame has expired. when the ac-link powers up it indicates readiness by way of the codec ready bits in the global status controller register. software needs to check those bits before accessing the codec. 3.8.6 ac ?7 link r eset acrst_l is asserted by the ic under the following conditions: reset_l asserted ac2c/mc3c[crst_l] asserted the ic never deasserts acrst_l automatically since after reset ac2c/mc3c[crst_l] defaults to zero. software has to deassert this bit. while ac2c/mc3c[crst_l] resides in the vdd_corex power plane, it remains cleared upon return from s3/s4/s5. 76functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.9 usb controller the usb 2.0 host controller is designed to comply with the ehci (enhanced host controller interface) speci?ation. it consists of three main components (see figure 16): ? the enhanced host controller (ehc): this block handles the usb 2.0 high speed traf?. additionally, it controls the port router. ? two companion host controllers . these are two ohci (open host controller interface) compliant host controllers (ohc0 & ohc1). these handle all usb1.1 compliant traf? and contain the legacy keyboard emulation (for non-usb aware environments). ? the port router . this block assigns the physical port interfaces to their respective owners. this ownership is controlled by ehc registers. per default, all ports are routed to the ohcx, in order to allow for a system with only usb 1.1 aware drivers to function. if a usb 2.0 aware driver is present in the system it will assign the ports to either an ohcx for low and full speed devices and hubs (usb 1.1 traf?) or to the ehc for high speed devices and hubs. figure 16. usb controller building blocks 3.9.1 usb interrupts all usb controllers drive the pirqd_l interrupt signal. however, the usb interrupt can be diverted to smi by the ohci-de?ed register hccontrol_interruptrouting. see section 3.4.2.1 on page 41 for data on routing of keyboard and mouse emulation interrupts. smi interrupts are also generated in response to accesses to i/o ports 60h and 64h and to irq1 and irq12 in support of the emulation logic. ohc0 3 ports ohc1 3 ports ehc 6 ports router ctrl port router to phy interface usb 1.1 traf? (low & full speed) usb 2.0 traf? (high speed) chapter 3 functional operation 77 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 3.10 lan ethernet controller 3.10.1 interface s 3.10.1.1 software interface the software interface to the network controller is divided into three parts. one part is the pci con?uration registers used to identify the network controller and to setup the con?uration of the device. the setup information includes the memory mapped i/o base address and the routing of the network controller interrupt channel. this allows for a jumperless implementation. the second portion of the software interface is the direct access to the i/o resources of the network controller. the host cpu accesses these registers for performance tuning, selecting options, statistics collecting, and starting transmissions. the third portion of the software interface is the descriptor and buffer areas that are shared between the software and the network controller during normal network operations. the descriptor area boundaries are set by the software and do not change during normal network operations. there is a separate descriptor area for each receive and transmit priority queue. the descriptor space contains relocatable pointers to the network frame data, and it is used to transfer frame status from the network controller to the software. the buffer areas are locations that hold frame data for transmission or that accept frame data that has been received. 3.10.1.2 network interface the network controller can be connected to an ieee 802.3 or proprietary network through the ieee 802.3-compliant media independent interface (mii). the mii is a nibble-wide interface to an external 100-mbit/s and/or 10-mbit/s transceiver device. the network controller supports both half-duplex and full-duplex operation on the network interface. 3.10.2 device operation 3.10.2.1 initialization before the network controller is ready for operation, several registers must be initialized. first certain read-only ?lds in pci con?uration space must be initialized by writing to alias registers in pci con?uration space. these ?lds contain values such as subsystem vendor id and maximum latency, which depend on the board in which the device is installed and should not be changed by operating system software. once these hardware parameters have been set up, the normal bios initialization software can write to the writable ?lds in pci con?uration space. in particular, the memory-mapped i/o base address register in con?uration space must be initialized before any of the memory-mapped registers can be accessed. 78 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information before any network frames can be sent or received, the unique 48-bit ieee mac address must be written to the physical address register (padr). normally this is done by a chipset initialization routine that runs before the network device driver is loaded. finally after the memory-mapped i/o base address register has been initialized and the operating system has been loaded, the device driver software can write to various memory-mapped registers to set up software parameters such as pointers to descriptor rings and the logical address filter contents. 3.10.2.2 re-initialization earlier members of the pcnet family of controllers had to be re-initialized if the transmitter and/or the receiver were not turned on during the original initialization, and it was subsequently required to activate them, or if either section was shut off due to the detection of a memory error, transmitter under?w, or transmit buffer error condition. this restriction does not apply to this controller. the memory error and transmit buffer error conditions cannot occur in the controller and the transmit under?w condition does not stop the controller's transmitter. 3.10.2.3 run and suspend following reset, the transmitter and receiver of the controller are disabled, so no descriptor or data dma activity can occur. the receiver does process incoming frames to detect address matches, which are counted in the rcvmisspkts register. no transmits occur except that pause frames may be sent (see ?w control section). setting the run bit in cmd0 causes the controller to begin descriptor polling and normal transmit and receive activity. clearing the run bit causes the controller to halt all transmit, receive, and dma transfer activities abruptly. the controller offers suspend modes that allow stopping the device with orderly termination of all network activity. transmit and receive are controlled separately. setting the rx_fast_spnd bit in cmd0 suspends receiver activity after the current frame being received by the mac is complete. if no frame is being received when rx_fast_spnd is set, the receiver is suspended immediately. after the receiver is suspended, the rx_suspended bit in stat0 is set and spndint interrupt bit in int0 is set. setting the rx_spnd bit in cmd0 suspends the receiver in the same way as rx_fast_spnd, but the rx_suspended bit and spndint interrupt bit are only set after any frames in the receive fifo have been completely transferred into system memory and the corresponding descriptors updated. no receive data or descriptor dma activity occurs while the receiver is suspended. when the receiver is suspended, no frames are received into the receive fifo, but frames are checked for address match and the rcvmisspkts counter incremented appropriately, and frames are checked for magic packet frame match if magic packet technology mode is enabled. setting the tx_fast_spnd bit in cmd0 suspends transmitter activity after the current frame being transmitted by the mac is complete. if no frame is being transmitted when tx_fast_spnd is set, chapter 3 functional operation 79 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the transmitter is suspended immediately. after the transmitter is suspended, the tx_suspended bit in stat0 is set and spndint interrupt bit in int0 is set. setting the tx_spnd bit in cmd0 suspends the transmitter in the same way as tx_fast_spnd, but the tx_suspended bit and spndint interrupt bit are only set after any frames in the transmit fifo have been completely transmitted. no transmit descriptor or data dma activity occurs while the transmitter is suspended. when the transmitter is suspended, no frames are transmitted except for ?w control frames (see flow control section). it is not meaningful to set both tx_spnd and tx_fast_spnd at the same time, nor is it meaningful to set both rx_spnd and rx_fast_spnd at the same time. doing so causes unpredictable results. however, transmit and receive are independent of each other, so one can be suspended or fast suspended while the other is running, suspended, or fast suspended. it is recommended when software polls this register that a delay be inserted between polls. continuous polling reduces the bus bandwidth available to the controller and delays completion of the suspend operation. it is recommended that software use the spndint interrupt to determine when the controller has suspended after one or more suspend bits have been set. this results in the least competition for the pci bus and thus the shortest time from setting of a suspend bit until completion of the suspend operation. the suspend bits can be used either to stop the transmitter or receiver while the controller is running or to prevent the transmitter or receiver from operating when the controller starts running. clearing the run bit in cmd0 generates a pulse that clears all the suspend command and status bits (tx_spnd, rx_spnd, tx_fast_spnd and rx_fast_spnd in cmd0, tx_suspended, and rx_suspended in stat0 and spndint in int0). to restart the controller with the transmitter disabled, set run and tx_spnd. to restart the controller with the receiver disabled, set run, rx_spnd, and rdmd0. since the suspend bit is cleared when run is cleared, the appropriate suspend bit must be set each time run is set. since the suspend bits and run are in the same register (cmd0), the suspend bit can be set at the same time that run is set. 3.10.2.4 descriptor management the network controller contains its own dma controller that automatically transfers network frame data between the network controller and buffers in host system memory. the actions of the dma controller are controlled by data structures in system memory called descriptors. each descriptor contains a pointer to a buffer in system memory plus several control and status ?lds. the descriptor management unit automatically reads control information from descriptors to determine how to manage the data transfers and writes back information about the status of the transfers. descriptor management is accomplished through message descriptor entries organized as ring structures in memory. there are ve descriptor rings, four for transmit and one for receive. the implementation of four descriptor rings for transmit allows the controller to provide improved support for quality of service. each descriptor ring is allocated to serve a certain class of traf?, with a clearly 80 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information de?ed priority scheme. the manner in which this scheme relates to standards such as ieee 802.1 p is described elsewhere in this document. this section simply describes the implementation of the descriptor rings themselves. each descriptor describes a single buffer. a frame may occupy one or more buffers. if multiple buffers are used, this is referred to as buffer chaining. transmit buffers can be of any size and can start at any byte address. receive buffers can start at any byte address, but there is a restriction on receive buffer length. either the length of a receive buffer must be a multiple of 4 bytes, or the length of the receive buffer must be at least as large as the longest frame that the software can accept. each descriptor ring must occupy a contiguous area of memory. the user-de?ed base addresses for the transmit and receive descriptor rings are set up during initialization in the badr0 and badx0-3 registers. the number of descriptors in each ring is written into the rcv_ring0_len and xmt_ringx_len registers, where x indicates the transmit ring number. the descriptor ring base addresses must be aligned to 16-byte boundaries. each ring entry is organized as four 32-bit message descriptors. ring lengths can be of any size up to 65535 descriptors. each ring entry contains the following information: the address of the actual message data buffer in user or host memory the length of the message buffer status information indicating the condition of the buffer see figure 32 on page 347 and figure 34 on page 349 for a detailed description of descriptor formats. to permit the queuing and de-queuing of message buffers, ownership of each buffer is allocated to either the network controller or the host. the own bit within the descriptor status information is used for this purpose. setting the own to 1 signi?s that the network controller currently has ownership of this descriptor and its associated buffer. only the owner is permitted to relinquish ownership or to write to any ?ld in the descriptor entry. a device that is not the current owner of a descriptor cannot assume ownership or change any ?ld in the entry. a device may, however, read from a descriptor that it does not currently own. software should always read descriptor entries in sequential order. when software ?ds that the current descriptor is owned by the network controller, the software must not read ahead to the next descriptor. the software should wait at a descriptor it does not own until the network controller sets own to 0 to release ownership to the software. figure 17 on page 81 illustrates the relationship between the receive and transmit descriptor ring base addresses, the receive and transmit descriptors, and the receive and transmit data buffers for one receive and one transmit descriptor ring. chapter 3 functional operation 81 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 17. receive and transmit descriptor rings 3.10.2.5 polling polling is the action that the descriptor management unit (dmu) takes when it reads a descriptor to examine the descriptor s own bit. polling is initiated either by a command from the host cpu or automatically as part of the frame processing sequence. when the dmu reads a descriptor from system memory, it reads more than one descriptor in one burst, so that polling can often be done by examining an internal descriptor cache. however, when the data buffer n-1 data buffer 0 data buffer 1 data buffer 2 rcv_ring0_len badr0 badr0 + 16 * rcv_ring0_len rcv descriptor ring 0 receive data buffers rcv descriptor 0 rcv descriptor 1 rcv descriptor 2 rcv descriptor n-1 data buffer n-1 data buffer 0 data buffer 1 data buffer 2 xmt_ring0_len badx0 badx0 + 16 * xmt_ring0_len xmt descriptor ring 0 transmit data buffers xmt descriptor 0 xmt descriptor 1 xmt descriptor 2 xmt descriptor n-1 82 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information dmu ?ds that the own bit of the next descriptor in the internal descriptor cache is 0, it must access the host system memory again to read in another block of descriptors. 3.10.2.6 transmit polling after the host cpu has ?led one or more buffers with data to be transmitted and has set the own bits of the descriptors that correspond to these buffers, it starts the transmit process by setting the transmit demand (tdmdx) bit in cmd0 that corresponds to the appropriate descriptor ring. (the ??in tdmdx is the number of the descriptor ring.) setting tdmdx causes the dmu to poll transmit descriptor ring number x if it does not already own a descriptor in that ring. responding to the tdmdx bit, the dmu begins the process of reading descriptors, checking own bits, retrieving buffer addresses, and copying frame data from transmit buffers to the transmit fifo. after the controller has ?ished copying the data from the buffer, it writes to system memory to clear the descriptor s own bit. it then polls the next descriptor in the ring. when the dmu encounters a descriptor whose own bit is not set, it stops polling and waits for the host cpu to set a tdmdx bit again. if the dmu encounters a descriptor whose own bit is set, but whose start of packet (stp) bit is not set, the controller immediately requests the bus in order to clear the own bit of this descriptor. after resetting the own bit of this descriptor, the controller immediately polls the next descriptor in the ring. similarly, when the dmu encounters a descriptor whose own bit is set, but whose byte count ?ld is 0, it also clears the descriptor s own bit and then polls the next descriptor in the ring. the network controller returns ownership of transmit descriptors to the software when the dma transfer of data from system memory to the controller's internal fifo is complete. this is different from older devices in the pcnet family, which do not return the last transmit descriptor of a frame (the one with enp=1) until transmission of the frame is complete. this controller does not return any status information in the transmit descriptor, it only writes to the own bit to clear it. if under?w occurs due to delays in setting the own bits or excessive bus latency, the transmitter appends an inverted fcs ?ld to the frame and increments the xmtunderrunpkts counter. the frame may be retransmitted (if the rex_uflo bit in cmd2 is set) or discarded. if an error occurs in the transmission that causes the frame to be discarded (late collision, under?w or retry failure with the corresponding retry or retransmit option not enabled) before the entire frame has been transferred or if the current transmit descriptor has its kill bit set, and if current transmit descriptor does not have its enp bit set, the controller skips over the rest of the frame that experienced the error. the controller clears the own bit for all descriptors with own = 1 and stp = 0 and continues in like manner until a descriptor with own = 0 (no more transmit frames in the ring) or own = 1 and stp = 1 (the ?st buffer of a new frame) is reached. at the end of any transmit operation, whether successful or with errors, the controller always performs another polling operation, unless the next transmit descriptor is already known to be owned. chapter 3 functional operation 83 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information whenever the dma controller ?ishes copying a transmit frame from system memory, it sets the tintx bit of int0 that corresponds to the descriptor ring number to indicate that the buffers are no longer needed. this causes an interrupt signal if the intren bit of cmd0 the corresponding tintenx bit of inten0 have been set. 3.10.2.7 receive polling the receive polling process is also started by the host cpu when it sets the receive demand (rdmd) bit in the cmd0 register. whenever the host cpu releases a receive buffer or group of receive buffers to the controller, it must set the rdmd bit. if the controller does not already own a receive buffer, the dmu polls the receive descriptor ring when rdmd is set. when a frame arrives from the network, the controller copies the frame to the next available receive buffer and then automatically polls the next descriptor. the network controller provides a means to reduce the number of transmit interrupts by postponing the interrupt to the cpu until a programmable number of interrupt events have occurred or a programmable amount of time has elapsed since the ?st interrupt event occurred. see section 3.10.15 on page 123. when receive activity is present on the channel, the controller waits until 64 bytes have been received. if the frame is accepted based on all active addressing schemes at that time, the dmu is noti?d that a frame has been received. as receive buffers become available in system memory, the dma controller copies frame data from the receive fifo into system memory. the controller sets the stp bit in the ?st descriptor of a frame. if the frame length exceeds the length of the current buffer, the controller passes ownership back to the system by writing 0s to the own and enp bits of the descriptor when the ?st buffer is full. this activity continues until the controller recognizes the completion of the frame (the last byte of this receive message has been removed from the fifo). the controller subsequently updates the current receive descriptor with the frame status (message byte count, vlan info, error ?gs, etc.) and sets the enp bit to 1. the controller then advances the internal ring pointer to make the next receive descriptor the new current receive descriptor. if the driver does not provide the network controller with a descriptor in a timely fashion, the receive fifo will eventually over?w. subsequent frames are discarded and the rcvmisspkts mib counter is incremented. normal receive operation resumes when a descriptor is provided to the controller and suf?ient data has been transferred from the network controller's receive fifo into the system memory. 3.10.3 software interrupt timer the network controller is equipped with a software programmable free-running interrupt timer. the timer is constantly running and generates an interrupt stint (int0, bit 4) when stinten (inten0, bit 4) is set to 1. after generating the interrupt, the software timer loads the value stored in stval and restarts. the timer value stval is interpreted as an unsigned number with a resolution of 10.24 s. for instance, a value of 98 (62h) corresponds to 1.0 ms. the default value of stval is 84 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information ffffh which corresponds to 0.671 seconds. a write to stval restarts the timer with the new contents of stval. 3.10.4 media access control the media access control (mac) engine incorporates the essential protocol requirements for operation of an ethernet/ieee 802.3-compliant node and provides the interface between the fifo subsystem and the mii. this section describes operation of the mac engine when operating in half-duplex mode. the operation of the device in full-duplex mode is described in the section titled full-duplex operation . the mac engine is compliant to section 4 of ieee standard 802.3, 1998 edition. the mac engine provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. these features include the ability to disable retries after a collision, dynamic fcs generation on a frame-by-frame basis, automatic pad ?ld insertion and deletion to enforce minimum frame size attributes, automatic retransmission without reloading the fifo, and automatic deletion of collision fragments. the mac also provides a mechanism for automatically inserting, deleting, and modifying ieee 802.3ac vlan tags. the two primary attributes of the mac engine are: transmit and receive message data encapsulation framing (frame boundary delimitation, frame synchronization) addressing (source and destination address handling) error detection (physical medium transmission errors) media access management medium allocation (collision avoidance, except in full-duplex operation) contention resolution (collision handling, except in full-duplex operation) 3.10.4.1 transmit and receive message data encapsulation the mac engine provides minimum frame size enforcement for transmit and receive frames. when apad_xmt (cmd2, bit 6) is set to 1, transmit messages are padded with suf?ient bytes (containing 00h) to ensure that the receiving station will observe an information ?ld (destination address, source address, length/type, data, and fcs) of 64 bytes. when astrp_rcv (cmd2, bit 13) is set to 1, the receiver automatically strips pad bytes from the received message by observing the value in the length ?ld and by stripping excess bytes if this value is below the minimum data size (46 bytes). both features can be independently over-ridden to allow messages shorter than the minimum frame size (less than 64 bytes of frame data) to be transmitted and/or received. the use of this feature reduces bus utilization because the pad bytes are not transferred into or out of main memory. chapter 3 functional operation 85 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 3.10.4.1.1 framing the mac engine autonomously handles the construction of the transmit frame. once the transmit fifo has been ?led to the predetermined threshold and access to the channel is currently permitted, the mac engine commences the 7-byte preamble sequence (a repeating 10101010 sequence, where ?st bit transmitted is a 1). the mac engine subsequently appends the start frame delimiter (sfd) sequence (10101011) followed by the serialized data from the transmit fifo. once the data has been transmitted, the mac engine appends the fcs (most signi?ant bit ?st) which was computed on the entire frame, starting with the destination address. the user is responsible for the correct ordering and content of the destination address, source address, length/type, and frame data ?lds of the frame. the receiver section of the mac engine detects the incoming preamble sequence when the rx_dv signal is activated by the external phy. the mac discards the preamble and begins searching for the sfd. (in the case of 100base-t4, for which there is no preamble to discard, the sfd is the ?st two nibbles received.) once the sfd is detected, all subsequent nibbles are treated as part of the frame. if automatic pad stripping is enabled, the mac engine inspects the length ?ld so that it can strip unnecessary pad characters and pass the remaining bytes through the receive fifo to the host. if pad stripping is performed, the mac engine also strips the received fcs bytes, although normal fcs computation and checking do occur. note that apart from pad stripping, the frame is passed unmodi?d to the host. if the length ?ld has a value of 46 or greater, all frame bytes including fcs are passed unmodi?d to the receive buffer, regardless of the actual frame length. if the frame terminates or suffers a collision before 64 bytes of information (after sfd) have been received, the mac engine automatically deletes the frame from the receive fifo, without host intervention. the network controller has the ability to accept runt packets for diagnostic purposes and proprietary networks. 3.10.4.2 destination address handling the ?st 6 bytes of information after sfd is interpreted as the destination address ?ld. the mac engine provides facilities for physical (unicast), logical (multicast), and broadcast address reception. 3.10.4.2.1 error detection the mac engine provides several facilities which count and recover from errors on the medium. in addition, it protects the network from gross errors due to inability of the host to keep pace with the mac engine activity. on completion of transmission, the mac engine updates various counters that are described in the statistics counters section. the host cpu can read these counters at any time for network management purposes. the mac engine also attempts to prevent the creation of any network error due to the inability of the host to service the mac engine. during transmission, if the host fails to keep the transmit fifo ?led suf?iently, causing an under?w, the mac engine ensures the message is sent with an invalid fcs, which causes the receiver to reject the message. 86functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information the mac engine can be programmed to try to transmit the same frame again after a fifo under?w. the transmitter backoff logic can also be programmed to treat late collisions just like normal collisions. the status of each receive message is available in the appropriate receive message descriptor (rmd). all received frames are passed to the host regardless of any error. during the reception, the fcs is generated on every nibble (including the dribbling bits) coming from the mii, although the internally saved fcs value is only updated on each byte boundary. the mac engine ignores an extra nibble at the end of a message, which corresponds to dribbling bits on the network medium. a framing or alignment error is reported to the user if an fcs error is detected and there is an extra nibble in the message. if there is an extra nibble but no fcs error, no framing error is reported. 3.10.4.3 media access management a basic requirement for all stations on the network is to provide fair access to the network. the ieee 802.3/ethernet protocols de?e a media access mechanism which permits all stations to access the channel with equality. any node can attempt to contend for the channel by waiting for a predetermined time (inter packet gap) after the last activity, before transmitting on the media. the channel is a multidrop communications medium (with various topological con?urations permitted), which allows a single station to transmit and all other stations to receive. if two nodes simultaneously contend for the channel, their signals interact causing loss of data, de?ed as a collision. it is the responsibility of the mac to attempt to avoid and to recover from collisions. 3.10.4.3.1 medium allocation the ieee standard 802.3, 1998 edition, requires that the csma/cd mac monitor the medium for traf? by watching for carrier activity. when carrier is detected, the medium is considered busy, and the mac should defer to the existing message. the standard allows an optional two-part deferral after a receive message. for details, see the ieee standard 802.3, 1998 edition, 4.2.3.2.1. the mac engine implements the optional receive two part deferral algorithm, with an interframespacing-part1 (ifs1) time of 60 bit times and an interframespacingpart 2 time of 36 bit times. the inter packet gap (ipg) timer starts timing the 96-bit interframespacing after the receive carrier is deasserted. during the ?st part deferral (ifs1), the mac engine defers any pending transmit frame and responds to the receive message. if carrier sense or collision is detected during the ?st part of the gap, the ipg counter is cleared to 0 continuously until carrier sense and collision are both deasserted, at which point the ipg counter resumes the 96-bit time count once again. once the ipg counter reaches the ifs1 count (60-bit times), the mac engine does not defer to a receive frame if a transmit frame is pending. instead, when the ipg count reaches 96-bit times, the transmitter starts transmitting, which causes a collision. the mac engine completes the preamble (64-bit) and jam (32-bit) sequence before ceasing transmission and invoking the random backoff algorithm. chapter 3 functional operation 87 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the mac engine allows the user to program both the ipg and the ?st part deferral (ifs1) through the ifs and ifs1 registers. the user can change the ipg value from its default of 96-bit times to compensate for delays through the external phy device. changing ifs1 alters the period for which the mac engine defers to incoming receive frames. note: care must be exercised when altering these parameters. undesirable network activity could result! this transmit two-part deferral algorithm is implemented as an option which can be disabled using the dxmt2pd bit (cmd2, bit 10). when dxmt2pd is set to 1, the ifs1 register is ignored, and the value 0 is used for the inter framespacingpart1 parameter. however, the ipg value is still valid. when the mac engine device operates in full-duplex mode, the ipg timer starts counting when tx_en is de-asserted. crs is ignored in full-duplex mode. 3.10.4.3.2 signal quality error (sqe) test during the time period immediately after a transmission has been completed, an external transceiver operating in the 10 mb/s half-duplex mode should generate an sqe test signal on the col pin within 0.6 s to 1.6 s after the transmission ceases. therefore, when the network controller is operating in half-duplex mode, the ipg counter ignores the col signal during the ?st 40-bit times of the inter- packet gap. this 40-bit times is the time period in which the sqe test message is expected. the sqe test was originally designed to check the integrity of the collision detection mechanism independently of the transmit and receive capabilities of the physical layer. however, mii-based phy devices detect collisions by sensing receptions that occur during transmissions, a process that does not require a separate level-sensing collision detection mechanism. collision detection is therefore dependent on the health of the receive channel. since the link monitor function checks the health of the receive channel, the sqe test is not very useful for mii-based devices. therefore, the device does not report or count sqe test failures. 3.10.4.3.3 collision handling collision detection is performed and reported to the mac engine through the col input pin. since the col signal is not required to be synchronized with tx_clk when the device is operating in half- duplex mode, the col signal must be asserted for at least three tx_clk cycles in order to be detected reliably. if a collision is detected before the complete preamble/sfd sequence has been transmitted, the mac engine completes the preamble/sfd before appending the jam sequence. if a collision is detected after the preamble/sfd has been completed, but before 512 bits have been transmitted, the mac engine aborts the transmission and appends the jam sequence immediately. the jam sequence is a 32- bit all zeros pattern. the mac engine attempts to transmit a frame a total of 16 times (initial attempt plus 15 retries) due to normal collisions (those within the slot time). detection of collision causes the transmission to be rescheduled to a time determined by the random backoff algorithm. if a single retry was required, the 88 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information xmtonecollision counter is incremented. if more than one retry was required, the xmtmultiplecollision counter is incremented. if all 16 attempts experienced collisions, the xmtexcessivecollision counter is incremented. after an excessive collision error, the transmit message is ?shed from the fifo. if retries have been disabled by setting the drty bit in the cmd2 register, the mac engine abandons transmission of the frame on detection of the ?st collision. in this case, xmtexcessivecollision counter is incremented, and the transmit message is ?shed from the fifo. if a collision is detected after 512-bit times have been transmitted, the collision is termed a late collision. the mac engine aborts the transmission, appends the jam sequence, and increments the xmtlatecollision counter. no retry attempt is scheduled on detection of a late collision. the transmit message is ?shed from the fifo. the ieee 802.3 standard requires use of a ?runcated binary exponential backoff?algorithm, which provides a controlled pseudo random mechanism to enforce the collision backoff interval, before retransmission is attempted. for details, see ieee standard 802.3, 1998 edition, 4.2.3.2.5. the mac engine provides an alternative algorithm, which suspends the counting of the slot time/ipg during the time that receive carrier sense is detected. this aids in networks where large numbers of nodes are present, and numerous nodes can be in collision. it effectively accelerates the increase in the backoff time in busy networks and allows nodes not involved in the collision to access the channel, while the colliding nodes await a reduction in channel activity. once channel activity is reduced, the nodes resolving the collision time-out their slot time counters as normal. this modi?d backoff algorithm is enabled when emba (cmd2, bit 11) is set to 1. 3.10.5 transmit operation the transmit operation and features of the network controller are controlled by programmable options. the controller provides a large transmit fifo to provide frame buffering for increased system latency, automatic retransmission with no fifo reload, and automatic transmit padding. 3.10.5.1 transmit function programming automatic transmit features such as retry on collision, fcs generation/transmission, and pad ?ld insertion can all be programmed to provide ?xibility in the (re-) transmission of messages. automatic pad ?ld insertion is controlled by the apad_xmt bit in the cmd2 register. the fcs generation/transmission feature can be programmed as a static feature (dxmtfcs bit in cmd2) or dynamically on a frame-by-frame basis (add_fcs bit in the transmit descriptor). rex_uflo (cmd2, bit 1) can be programmed to cause the transmitter to automatically restart the transmission process instead of discarding a frame that experiences an under?w error. after an under?w error the retransmission does not begin until the entire frame has been loaded into the transmit fifo. chapter 3 functional operation 89 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information transmit start point (xmtsp) in ctrl1 sets the point when the transmitter actually attempts to transmit a frame onto the media. a minimum of xmtsp bytes must be written to the transmit fifo for the current frame before transmission of the current frame will begin. (when automatically padded packets are being sent, it is conceivable that the xmtsp is not reached when all of the data has been transferred to the fifo. in this case, the transmission begins when all of the frame data has been placed into the transmit fifo.) the default value of xmtsp is 01b, meaning there has to be 64 bytes in the transmit fifo to start a transmission. in order to ensure that collisions occurring within 512 bit times from the start of transmission (including preamble) are automatically retried with no host intervention, the transmit fifo ensures that data contained within the fifo is not overwritten until at least 64 bytes (512 bits) of preamble plus address, length, and data ?lds have been transmitted onto the network without encountering a collision. if the rex_uflo bit is set, the transmit data is not overwritten until the frame has been either transmitted or discarded. in a (nonstandard) system that allows frames that are larger than the transmit fifo size, the xmtsp bit should not be set to 01b (full frame), and the rex_uflo bit should not be set. 3.10.5.1.1 automatic pad generation transmit frames can be automatically padded to extend them to 64 data bytes (excluding preamble). this allows the minimum frame size of 64 bytes (512 bits) for ieee 802.3/ethernet to be ensured with no software intervention from the host/controlling process. setting the apad_xmt bit in cmd2 enables the automatic padding feature. the pad is placed between the llc data ?ld and fcs ?ld in the ieee 802.3 frame. fcs is always added if the frame is padded, regardless of the state of dxmtfcs (cmd2, bit 8) or add_fcs (in the transmit descriptor). the transmit frame is padded by bytes with the value of 00h. the default value of apad_xmt is 0 after h_reset, which disables automatic pad generation. if automatic pad generation is disabled, the software is responsible for insuring that the minimum frame size requirement is met. the hardware can reliably transmit frames ranging in size from 16 to 65536 octets. it is the responsibility of upper layer software to correctly de?e the actual length/type ?ld contained in the message to correspond to the total number of llc data bytes encapsulated in the frame (length/type ?ld as de?ed in the ieee 802.3 standard). the length value contained in the message is not used by the network controller to compute the actual number of pad bytes to be inserted. the controller appends pad bytes dependent on the actual number of bits transmitted onto the network. once the last data byte of the frame has completed, prior to appending the fcs, the controller checks to ensure that 544 bits have been transmitted. if not, pad bytes are added to extend the frame size to this value, and the fcs is then added. see figure 18. 90 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information figure 18. iso 8802-3 (ieee/ansi 802.3) data frame the 544 bit count is derived from the following: ? minimum frame size (excluding preamble/sfd, including fcs) 64 bytes or 512 bits ? preamble/sfd size: 8 bytes or 64 bits ? fcs size: 4 bytes or 32 bits at the point that fcs is to be appended, the transmitted frame should contain: ? preamble/sfd + (min frame size C fcs): 64 + (512-32) = 544 bits a minimum length transmit frame from the network controller, therefore, is 576 bits, after the fcs is appended. 3.10.5.2 transmit fcs generation automatic generation and transmission of fcs for a transmit frame depends on the value of dxmtfcs (cmd2, bit 8). if dxmtfcs is cleared to 0, the transmitter generates and appends the fcs to the transmitted frame. if the transmitter modi?s the frame data because of automatic padding or vlan tag manipulation, it appends the fcs regardless of the state of dxmtfcs or add_fcs (in the transmit descriptor). note that the calculated fcs is transmitted most signi?ant bit ?st. the default value of dxmtfcs is 0 after h_reset. when dxmtfcs is set to 1, the add_fcs bit in the transmit descriptor allows the automatic generation and transmission of fcs on a frame-by-frame basis. when dxmtfcs is set to 1, a valid fcs ?ld is appended only to those frames whose tx descriptors have their add_fcs bits set to 1. if a frame is split into more than one buffer, the add_fcs bit is ignored in all descriptors except for the ?st. 3.10.5.3 transmit error conditions the transmitter detects the following error conditions and increments the appropriate error counters when they occur: ? loss of carrier ? late collision preamble 1010....1010 sfd 10101011 destination address source address length/ type llc data pad fcs 56 bits 8 bits 6 bytes 6 bytes 2 bytes 4 bytes 46?500 bytes chapter 3 functional operation 91 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information ? transmit fifo under?ow late collision errors can only occur when the device is operating in half-duplex mode. loss of carrier and transmit fifo under?w errors are possible when the device is operating in half- or full-duplex mode. when a late collision or under?w error occurs in the middle of a multi-buffer frame transmission, the appropriate error counter is incremented, and the transmission is aborted with an inverted fcs ?ld appended to the frame. the own bits in the current and subsequent descriptors are cleared until the stp bit is found, indicating the start of the next frame. if rex_uflo (cmd2, bit 1) is set, the transmitter does not ?sh the frame data from the transmit fifo after a transmit fifo under?w error occurs. instead, it waits until the entire frame has been copied into the transmit fifo, and then it restarts the transmission process. 3.10.5.3.1 loss of carrier the xmtlosscarrier counter is incremented if transmit is attempted when the link_stat bit in the stat0 register is 0. the link_stat bit is set automatically during the auto-negotiation process when the external phy device determines that the link is up. alternatively the software can bypass the auto-negotiation process by clearing the en_pmgr bit in cmd3 and setting force_link_status, also in cmd3. 3.10.5.3.2 late collision a late collision is detected when the device is operating in half-duplex mode and a collision condition occurs after one slot time (512 bit times) after the transmit process was initiated (?st bit of preamble commenced). when it detects a late collision, the controller increments the xmtlatecollision counter. the controller abandons the transmit process for that frame and processes the next transmit frame in the ring. 3.10.5.3.3 transmit fifo under?w an under?w error occurs when the transmitter runs out of data from the transmit fifo in the middle of a transmission. when this happens, an inverted fcs is appended to the frame so that the intended lan ethernet receiver will ignore the frame, and the xmtunderrunpkts counter is incremented. if rex_uflo (cmd2, bit 1) is set to 1, the transmitter then waits until the entire frame has been loaded into the transmit fifo, and then it restarts the transmission of the same frame. if the rex_uflo is cleared to 0, the transmitter does not attempt to retransmit the aborted frame. the rex_uflo bit should not be set in a (nonstandard) system that allows frames that are larger than the transmit fifo size. 92 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.10.5.4 conduit mode the conduit mode of operation allows the lan ethernet controller to pass frame data to an external mac-type device attached to the mii bus. this option eliminates the need for a frame buffer in the external device. in this mode the backoff logic is disabled, and the col and crs signals from the mii are used to control transmit retry and frame discard. the internal synchronizers on the col and crs inputs are bypassed, and the external device must provide col and crs inputs that are synchronized with tx_clk. the crs signal is used for ?w control across the mii bus. the external device controls the local transmit mac by asserting crs after the local device asserts tx_en. crs is held on until the external device has ?ished processing the frame, preventing the local device from starting the transmission of the next frame. the current transmit frame is retained in the fifo until crs deasserts. if col is asserted at any time while crs is asserted, the frame is requeued and retransmitted. in conduit mode all mib counters work like they do in half duplex mode, except that the xmtexcessivecollision counter is incremented when col is asserted while crs is deasserted (as explained below), and not when a frame has experienced 16 unsuccessful transmission attempts. conduit mode is enabled by setting the conduit_mode bit (cmd2, bit 29). in conduit mode the mii handshake is modi?d as follows: 1. the crs and col inputs must be synchronized with tx_clk, changing state at the falling edge of tx_clk. in this mode crs and col must meet set-up and hold timing requirements with respect to the rising edge of tx_clk similar to the timing requirements for the synchronous signals in the mii receive path. 2. if col is asserted while crs is also asserted, the frame is requeued for transmission. the frame is not dropped when crs is deasserted. 3. if col is not asserted during the time that crs is asserted, the appropriate mib counters are incremented to indicate a successful transmission, and the frame is discarded from memory when crs is deasserted. 4. if col is asserted during the same tx_clk cycle in which crs is deasserted, the frame is discarded and counted as an excessive collision error. (the xmtexcessivecollision counter is incremented.) in this case crs must be held low for at least 2 tx_clk cycles. after 2 tx_clk cycles, crs may be asserted again to delay the transfer of the next frame over the mii. 5. following deassertion of crs, normal ipg is counted and next frame transmitted. the external device asserts crs when it sees tx_en asserted. figure 19 shows a frame that is requeued and then successfully transmitted. figure 20 shows a frame that is dropped because the external device reports excessive collisions. in this ?ure a second frame is transmitted successfully with no collisions. chapter 3 functional operation 93 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 19. conduit mode transmission with one collision figure 20. conduit mode excessive collisions error 3.10.6 receive operation the receive operation and features of the network controller are controlled by programmable options. the controller uses a large receive fifo to provide frame buffering for increased system latency, automatic ?shing of collision fragments (runt packets), automatic receive pad stripping, and a variety of address match options. 3.10.6.1 receive function programming automatic pad ?ld stripping is enabled by setting the astrp_rcv bit in cmd2. this can provide ?xibility in the reception of messages using the ieee 802.3 frame format. the device can be programmed to accept all receive frames regardless of destination address by setting the prom bit in cmd2. acceptance of unicast and broadcast frames can be individually turned off by setting the drcvpa or drcvbc bits in cmd2. the physical address register stores the address that the mac receiver compares to the destination address of the incoming frame for a unicast address match. the logical address filter register serves as a hash ?ter for multicast address matching. tx_en txd[3:0] crs col frame1 frame1 requeue frame 1 increment xmtcollisions end of frame 1 increment good frame counters tx_en txd[3:0] crs col frame1 frame2 flush frame 1 increment xmtexcessivecollision end of frame 2 increment good frame counters 94 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information for test purposes, the controller can be programmed to accept runt packets of 12 bytes or larger by setting rpa in cmd2. 3.10.6.2 address matching mac addresses are classi?d as either unicast, multicast, or broadcast. the least signi?ant bit of the ?st octet of a mac address (the i/g bit) indicates whether the address is unicast (individual) or multicast (group). if the bit is 0, the address is an individual address and is intended to be received by a single network station. if the bit is 1, the address is a group address and is intended to be received by more than one network station. the special address that consists of all 1s is known as the broadcast address. frames addressed to the broadcast address are intended to be received by all stations on the local area network. the network controller contains three address matching mechanisms that determine which incoming frames it will receive: 1. the physical address match comparator 2. the broadcast address match comparator 3. the multicast hash filter in addition if the promiscuous mode bit (prom, cmd2, bit 16) is set, all valid frames are received. an incoming frame is saved in system memory if any one of these mechanisms signals a match for that frame. the physical address match comparator signals a match if the destination address (da) ?ld of the incoming frame exactly matches the contents of the physical address register (padr). the byte ordering is such that the ?st byte received from the network (after the sfd) must match the least signi?ant byte of padr (padr[7:0]), and the sixth byte received must match the most signi?ant byte of padr (padr[47:40]). the physical address match comparator can be disabled by setting the disable receive physical address match (drcvpa) bit in the cmd2 register. the broadcast address match comparator signals a match if the destination address (da) ?ld of the incoming frame is all ones. the broadcast address match comparator can be disabled by setting the disable receive broadcast address match (drcvbc) bit in the cmd2 register. if drcvbc is set and prom is cleared, no broadcast frames are received even if another address match function signals a match. 3.10.6.2.1 the logical address filter if the least signi?ant bit of the ?st octet of a mac address (as transmitted over the network) is a 1, the address is a multicast (or logical) address that indicates that the frame is meant to be received by more than one network node. the network controller can be programmed to accept frames addressed to any number of multicast addresses. the logical address filter is used to ?ter out unwanted multicast frames. chapter 3 functional operation 95 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the logical address filter block consists of a 64-bit logical address filter table and associated control logic. the logical address filter logic uses the crc generator from the frame check sequence block to perform a calculation on the da ?ld of a frame to determine whether or not to signal a match. the crc generator calculates a crc value for the da ?ld of the frame. if the destination address is a multicast address, the 6 most signi?ant bits of this crc value are used as a pointer to a bit in the logical address filter table. if the selected bit is 1, the logical address filter signals a match. see figure 21 on page 96. the broadcast address (all ones) is treated as a special case, not as an instance of a multicast address. a frame addressed to the broadcast address does not cause a multicast address match. this means that if the drcvbc bit is set, broadcast frames are not received even if the bit in the logical address filter that corresponds to the broadcast address is set. the host cpu can read and write the logical address filter register directly. although the logical address filter rejects the vast majority of addresses that are not intended for this device, it is not a perfect ?ter. more than one multicast address maps to each bit in the ?ter table. therefore the host software must compare the da ?ld of each frame that was accepted by the logical address filter with a software table of acceptable multicast addresses. if the logical address filter signals a match for an incoming frame, the logical address filter match (lafm) bit is set in the receive descriptor that corresponds to the frame. the host cpu can examine this bit to determine whether or not it should look up the destination address in the software address table. 3.10.6.2.2 address match classi?ation the receive descriptor associated with a frame includes 3 bits that indicate why the frame was received. the physical address match (pam) bit is set when the destination address matches the contents of the padr. the logical address filter match (lafm) bit is set when the destination address is a multicast address that causes the multicast hash filter to signal a match and the destination address is not the broadcast address. the broadcast address match (bam) bit is set when the destination address is the broadcast address. 96functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information figure 21. address match logic 3.10.6.3 automatic pad stripping during reception of an ieee 802.3 frame, the pad ?ld can be stripped automatically. setting astrp_rcv (cmd2, bit 13) to 1 enables the automatic pad stripping feature. the pad ?ld is stripped before the frame is passed to the fifo, thus preserving fifo space for additional frames. the fcs ?ld is veri?d, but it is also stripped, because it was computed at the transmitting station based on the data and pad ?ld characters, and is invalid for a receive frame that has had the pad characters stripped. the number of bytes to be stripped is calculated from the embedded length ?ld (as de?ed in the ieee standard 802.3) contained in the frame. the length indicates the actual number of llc data bytes contained in the message. any received frame that contains a length ?ld less than 46 bytes has the pad ?ld stripped (if astrp_rcv is set). receive frames that have a length ?ld of 46 bytes or greater are passed to the host unmodi?d. figure 22 on page 97 shows the byte/bit ordering of the received length ?ld for an ieee 802.3-compatible frame format. 47 1 crc gen sel 31 26 mux 63 0 64 match = 1 packet accepted match = 0 packet rejected match logical address filter (ladrf) 0 6 32-bit resultant crc 1 0 received message destination address chapter 3 functional operation 97 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 22. ieee 802.3 frame and length field transmission order since any valid ethernet type ?ld value is greater than a valid ieee 802.3 length ?ld, the network controller does not attempt to strip valid ethernet frames. note: for some network protocols, the value passed in the ethernet type and/or ieee 802.3 length ?ld may not be compliant with either standard and may cause problems if pad stripping is enabled. 3.10.6.4 receive fcs checking reception and checking of the received fcs is performed automatically by the network controller. note that if the automatic pad stripping feature is enabled, the fcs for padded frames is veri?d against the value computed for the incoming bit stream including pad characters, but the fcs value for a padded frame is not passed to the host. if an fcs error is detected in any frame, the error is reported in the crc bit in the receive descriptor. 3.10.6.5 receive exception conditions the network controller detects and collects statistics on the following error conditions: fcs errors framing errors receiver over?w events preamble 1010....1010 sfd 10101011 destination address source address length llc data pad fcs 4 bytes 46 1500 bytes 2 bytes 6 bytes 6 bytes 8 bits 56 bits start of frame at time = 0 increasing time bit 0 bit 7 bit 0 bit 7 most significant byte least significant byte 1 1500 bytes 45 0 bytes 98 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information these error conditions are reported in the corresponding receive descriptors. the rcvfcserrors, rcvalignmenterrors, or rcvmisspkts counter is also incremented when one of these events occurs. 3.10.7 statistics counters in order to provide network management information with minimum host cpu overhead, the network controller automatically maintains a set of 32-bit controller statistics counters. the host cpu can access the statistics counters two ways; it can force all counters to be cleared in one operation, or it can read a single 32-bit counter in one operation. the host cpu can clear all counters by executing the following steps: 1. poll the mib_ cmd_active bit in the mib_addr register until this bit is 0. 2. set the mib_clear bit and clear the mib_rd_cmd bit in the mib_addr register. the mib_cmd_active bit is automatically cleared to 0 when the counters have all been cleared. the mib_clear command takes about 1.3 s. the host cpu can read any statistics counter indirectly through the mib_addr and mib_data registers as described in section 4.10.1 on page 306. the addresses that should be written to the mib- addr register are shown in table 27 on page 99 and table 28 on page 102. when the host cpu sets the rd_cmd bit in the mib_addr register, the controller loads the contents of the selected mib counter into the mib_data register between 210 ns and 2 s later. 3.10.7.1 receive statistics counters the receive statistics counters are de?ed and the management information base (mib) objects that they support are listed in table 26 on page 98. for these counters, a valid frame is de?ed as a frame that has a correct fcs value and whose length is between 64 octets and a maximum frame size that depends on the state of the jumbo and vsize bits (cmd3, bits 21 and 20). if both of these bits are 0, the maximum frame size is 1518 octets. setting the jumbo bit adds 7500 octets to the maximum frame size, and setting the vsize bit adds 4 octets. the maximum valid frame size is summarized in table 26 on page 98. frames longer than 9022 bytes can be received or transmitted successfully, but they are counted as oversized frames. however, frames longer than 65536 bytes might not be handled properly. table 26. maximum valid frame size jumbo vsize max. valid frame size (octets) 0 0 1518 0 1 1522 1 0 9018 1 1 9022 chapter 3 functional operation 99 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information in table 27 on page 99, the address column gives the value that the host cpu must write to the mib_addr register in order to read the counter. table 27. receive statistics counters addres s (hex) receive counter name mib object supported description of counter/comments 00 rcvmisspkts rmon etherstatsdropevents rmon etherhistorydropevents mib-ii ifindiscards e-like dot3statsinternalmacreceiveerrors the number of times a receive packet was dropped due to lack of resources. this includes the number of times a packet was dropped due to receive fifo over ow and lack of receive descriptor. this count does not include packets that are counted as undersize, oversize, misaligned or bad fcs packets. when run=0 any packet that is not a fragment and that passes the address match tests causes the rcvmisspkts counter to increment. 01 rcvoctets rmon etherstatsoctets rmon etherhistoryoctets mib-ii ifinoctets the total number of octets of data received including octets from invalid frames. this does not include the preamble but does include the fcs bits. the rcvoctets counter is incremented whenever the receiver receives an octet. 02 rcvbroadcastpkts rmon etherstatsbroadcastpkts rmon etherhistorybroadcastpkts ext-mib-ii ifinbroadcastpkts the total number of valid frames received that are addressed to a broadcast address. this counter does not include errored broadcast packets or valid multicast packets. 03 rcvmulticastpkts rmon etherstatsmulticastpkts rmon etherhistorymulticastpkts ext-mib-ii ifinmulticastpkts the total number of valid frames received that are addressed to a multicast address. this counter does not include errored multicast packets or valid broadcast packets. 04 rcvundersizepkts rmon etherstatsundersizepkts rmon etherhistoryundersizepkts the total number of valid frames received that are less than 64 bytes long (including the fcs) and do not have any error. sfd must be received so that the fcs can be calculated. 05 rcvoversizepkts rmon etherstatsoversizepkts rmon etherhistoryoversizepkts e-like mib dot3statsframetoolongs the total number of packets received that are greater than the maximum valid frame size (including the fcs) and do not have any error. sfd must be received so that the fcs can be calculated. 100 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 06 rcvfragments rmon etherstatsfragments rmon etherhistoryfragments the number of packets received that are less than 64 bytes (not including the preamble or sfd) and have either an fcs error or an alignment error. 07 rcvjabbers rmon etherstatsjabbers rmon etherhistoryjabbers the number of packets received that are greater than the maximum valid frame size and have either an fcs error or an alignment error. 08 rcvunicastpkts mib-ii ifinucastpkts the number of valid frames received that are not addressed to a multicast address or a broadcast address. this counter does not include errored unicast packets. 09 rcvalignmenterrors e-like mib dot3statsalignmenterrors the number of packets received that are between 64 and the maximum valid frame size (excluding preamble/sfd but including fcs), inclusive, and have a bad fcs with non-integral number of bytes. 0a rcvfcserrors e-like mib dot3statsfcserrors the total number of packets received that are between 64 and the maximum valid frame size (excluding preamble/sfd but including fcs), inclusive, and have a bad fcs with an integral number of bytes. this counter also counts packets with a correct fcs if rx_er occurs when valid carrier rx_dv is present. 0b rcvgoodoctets rmon hostinoctets rmon hosttimeinoctets the total number of bytes received by a port. bytes are 8-bit quantities received after the sfd. this does not include preamble or bytes from erroneous packets, but does include the fcs. 0c rcvmacctrl 802.3x amaccontrolframesreceived the total number of valid frames received with a lengthortype eld value equal to 8808h. 0d rcvflowctrl 802.3x apausemacctrlframesreceived the total number of valid frames received with (1) a lengthortype eld value equal to 8808h and (2) an opcode equal to 1. 0e rcvpkts64octets rmon etherstatspkts64octets the total number of packets received (including error packets) that are 64 bytes long. table 27. receive statistics counters (continued) addres s (hex) receive counter name mib object supported description of counter/comments chapter 3 functional operation 101 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 0f rcvpkts65to127octets rmon etherstatspkts65to127octets the total number of packets received (including error packets) that are 65 bytes to 127 bytes long, inclusive. 10 rcvpkts128to255octets rmon etherstatspkts128to255octets the total number of packets received (including error packets) that are 128 bytes to 255 bytes long, inclusive. 11 rcvpkts256to511octets rmon etherstatspkts256to511octets the total number of packets received (including error packets) that are 256 bytes to 511 bytes long, inclusive. 12 rcvpkts512to1023octets rmon etherstatspkts512to1023octets the total number of packets received (including error packets) that are 512 bytes to 1023 bytes long, inclusive 13 rcvpkts1024to1518octe ts rmon etherstatspkts1024to1518octets the total number of packets received (including error packets) that are 1024 bytes to 1518 (1522 when vlan set) bytes long, inclusive. 14 rcvunsupportedopcode s 802.3x an unsupportedopcodesreceived the total number of valid frames received with (1) a lengthortype eld value equal to 8808h and (2) an opcode not equal to 1. 15 rcvsymbolerrors the number of times when valid carrier (crs) was present and there was at least one occurrence of an invalid data symbol (rx_er). this counter is incremented only once per valid carrier event (once per frame), and if a collision is present, this counter must not be incremented. 16 rcvdroppktsring0 the number of packets that were dropped because no descriptor was available in receive descriptor ring 0 when it was needed. 17-19 reserved 1a rcvjumbopkts the total number of packets received (including error packets) that are 1519 bytes to 9018 bytes long, inclusive when vsize=0 or 1523 to 9022 when vsize=1. 1b-1f reserved table 27. receive statistics counters (continued) addres s (hex) receive counter name mib object supported description of counter/comments 102 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.10.7.2 transmit statistics counters table 28 on page 102 describes the statistics counters associated with the transmitter and lists the mib objects that these counters support. the address column gives the value that the host cpu must write to the mib_addr register in order to read the counter. table 28. transmit statistics counters addres s (hex) transmit counter name mib object supported description of counter/comments 20 xmtunderrunpkts rmon etherstatsdropevents rmon etherhistorydropevents mib-ii ifoutdiscards e-like dot3statsinternalmactranmsiterrors the number of times a packet was dropped due to transmit fifo underrun. 21 xmtoctets rmon etherstatsoctets rmon etherhistoryoctets rmon hostoutoctets rmon hosttimeoutoctets mib-ii ifoutoctets the total number of octets of data transmitted. this does not include the preamble but does include the fcs bits. the xmtoctets counter is incremented whenever the transmitter transmits an octet. 22 xmtpackets rmon etherstatspkts rmon etherhistorypkts rmon hostoutpkts rmon hosttimeoutpkts bridge-mib dot1dtpportoutframes the number of packets transmitted. this does not include packets transmitted with errors (i.e., collision fragments and partial packets due to transmit fifo under runs). 23 xmtbroadcastpkts rmon etherstatsbroadcastpkts rmon etherhistorybroadcastpkts rmon hostoutbroadcastpkts rmon hosttimeoutbroadcastpkts ext-mib-ii ifoutbroadcastpkts the number of valid frames transmitted that are addressed to a broadcast address. this counter does not include errored broadcast packets or valid multicast packets. 24 xmtmulticastpkts rmon etherstatsmulticastpkts rmon etherhistorymulticastpkts rmon hostoutmulticastpkts rmon hosttimeoutmulticastpkts ext-mib-ii ifoutmulticastpkts the number of valid frames transmitted that are addressed to a multicast address. this counter does not include errored multicast packets or valid broadcast packets. 25 xmtcollisions rmon etherstatscollisions rmon etherhistorycollisions the number of collisions that occur during transmission attempts. collisions that occur while the device is not transmitting (i.e., receive collisions) are not identi able and therefore not counted. chapter 3 functional operation 103 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 26 xmtunicastpkts mib-ii ifoutucastpkts the number of valid frames transmitted that are not addressed to a multicast or a broadcast address. this counter does not include errored unicast packets. 27 xmtonecollision e-like dot3statssinglecollisionframes the number of packets successfully transmitted after experiencing one collision. 28 xmtmultiplecollision e-like dot3statsmultiplecollsionframes the number of packets successfully transmitted after experiencing more than one collision. 29 xmtdeferredtransmit e-like dot3statsdeferredtransmissions the number of packets for which the rst transmission attempt on the network is delayed because the medium is busy. 2a xmtlatecollision e-like dot3statslatecollisions the number of late collisions that occur. a late collision is de ned as a collision that occurs more than 512 bit times after the transmission starts. the 512- bit interval is measured from the start of preamble. 2b xmtexcessivedefer the number of excessive deferrals that occur. an excessive deferral occurs when a transmission is deferred for more than 3036 byte times in normal mode or 3044 byte times in vlan mode. 2c xmtlosscarrier the number of transmit attempts made when the link_stat bit in the stat0 register is 0. 2d xmtexcessivecollision e-like dot3statsexcessivecollisions the number of packets that are not transmitted because the packet experienced 16 unsuccessful transmission attempts (the rst attempt plus 15 retries). 2e xmtbackpressure the total number of back pressure collisions generated. 2f xmtflowctrl pausemacctrlframestransmitted the total number of pause packets generated and transmitted by the controller hardware. 30 xmtpkts64octets rmon etherstatspkts64octets the total number of packets transmitted (excluding error packets) that are 64 bytes long. table 28. transmit statistics counters (continued) addres s (hex) transmit counter name mib object supported description of counter/comments 104 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.10.8 vlan support virtual bridged local area network (vlan) tags are de?ed in ieee standard 802.3ac-1998. a vlan tag is a 4-byte quantity that is inserted between the source address ?ld and the length/type ?ld of a basic 802.3 mac frame. the vlan tag consists of a length/type ?ld that contains the value 8100h and a 16-bit tag control information (tci) ?ld. the tci ?ld is further divided into a 3-bit user priority ?ld, a 1-bit canonical format indicator (cfi), and a 12-bit vlan identi?r. a frame that has no vlan tag is said to be untagged. a frame with a vlan tag whose vlan identi?r ?ld contains the value 0 is said to be priority-tagged. a frame with a vlan tag with a non- zero vlan identi?r ?ld is said to be vlan-tagged. the format of a vlan-tagged frame is shown in figure 23 on page 105. 31 xmtpkts65to127octets rmon etherstatspkts65to127octets the total number of packets transmitted (excluding error packets) that are 65 bytes to 127 bytes long, inclusive. 32 xmtpkts128to255octet s rmon etherstatspkts128to255octets the total number of packets transmitted (excluding error packets) that are 128 bytes to 255 bytes long, inclusive. 33 xmtpkts256to511octet s rmon etherstatspkts256to511octets the total number of packets transmitted (excluding error packets) that are 256 bytes to 511 bytes long, inclusive. 34 xmtpkts512to1023octe ts rmon etherstatspkts512to1023octets the total number of packets transmitted (excluding error packets) that are 512 bytes to 1023 bytes long, inclusive 35 xmtpkts1024to1518 octets rmon etherstatspkts1024to1518octets the total number of packets transmitted (excluding error packets) that are 1024 bytes to 1518 (1522 when vlan set) bytes long, inclusive. 36 xmtoversizepkts the total number of packets transmitted (excluding error packets) that are longer than the maximum valid frame size. 37 xmtjumbopkts the total number of packets transmitted (including error packets) that are 1519 bytes to 9018 bytes long, inclusive when vsize=0 or 1523 to 9022 when vsize=1. table 28. transmit statistics counters (continued) addres s (hex) transmit counter name mib object supported description of counter/comments chapter 3 functional operation 105 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 23. vlan-tagged frame format the network controller includes several features that can simplify the processing of ieee 802.3ac vlan-tagged frames. 3.10.8.1 vlan frame size since the vlan tag contains 4 octets, in networks that allow vlan tags, the maximum valid frame size is increased by 4 octets from 1518 to 1522 octets. in networks that support 9018-octet jumbo frames, adding vlan capability increases the maximum valid frame size from 9018 to 9022 octets. the maximum valid frame size is programmed using the vsize and jumbo bits (cmd3, bits 20 and 21) as shown in table 26 on page 98. the maximum valid frame size is used for determining when to increment the xmtoversizepkts, xmtpkts1024to1518octets, xmtexcessivedefer, rcvjabbers, rcvalignmenterrors, rcvfcserrors, rcvpkts1024to1518octets, and rcvoversizepkts mib counters. the maximum frame size does not affect whether or not a frame is actually received. 3.10.8.2 admit only vlan frames option the admit only vlan (vlonly) bit in the command3 register can be programmed to reject any frame that is not vlan-tagged. when vlonly is set, untagged or priority-tagged frames are ?shed from the receive fifo and are not copied into system memory. only frames with a length/type ?ld equal to 8100h and a non-zero vlan id ?ld are received. the vlan id ?ld consists of bits [11:0] of the 15th and 16th bytes of the frame. 3.10.8.3 vlan tags in descriptors vlan tag information can be passed between the host cpu and the network medium through transmit or receive descriptors. the transmitter can be programmed to insert or delete a vlan tag preamble sfd destination address source address length/type = 8100h tag control information mac client length/type mac client data frame check sequence 7 octets 1 octet 6 octets 6 octets 2 octets 2 octets 2 octets 42-1500 octets 4 octets vlan id canonical fmt indicator user priority 0 11 13 15 106functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information or to modify the tci ?ld of a vlan tag. this feature allows vlan software to control the vlan tag of a frame without modifying data in transmit buffers. the receiver can determine whether a frame is untagged, priority-tagged, or vlan-tagged, and it can copy the tci ?ld of the vlan tag into the receive descriptor and remove the tag from the frame. the tag control command (tcc) is a 2-bit ?ld in the transmit descriptor that determines whether the transmitter will insert, delete, or modify a vlan tag or transmit the data from the transmit buffers unaltered. the encoding of the tcc ?ld is shown in table 29 on page 106. if the transmitter adds, deletes, or modi?s a vlan tag, it appends a valid fcs ?ld to the frame, regardless of the state of the disable transmit fcs (dxmtfcs) bit (cmd2, bit 8). the receiver examines each incoming frame and writes the frame s vlan classi?ation into the tag type (tt) ?ld of the receive descriptor. if the frame contains a vlan tag, the receiver copies the tci ?ld of tag into the tci ?ld of the receive descriptor. the encoding of the tt ?ld is shown in table 30. if the vl_tag_del bit in cmd3 is set, the controller deletes the 4-byte tag from the frame as it copies the frame to host system memory. 3.10.9 loopback operation loopback is a mode of operation intended for system diagnostics. in this mode, the transmitter and receiver are both operating at the same time so that the controller receives its own transmissions. the controller provides two basic types of loopback. in internal loopback mode, the transmitted data is looped back to the receiver inside the controller without actually transmitting any data to the external network. the receiver moves the received data to the next receive buffer, where it can be examined by table 29. vlan tag control command tcc (tmd2[17:16]) action 00 transmit data in buffer unaltered 01 delete tag header 10 insert tag header containing tci eld from descriptor. 11 replace tci eld from buffer with tci data from descriptor. table 30. vlan tag type tt (rmd1[19:18]) description 00 reserved 01 frame is untagged 10 frame is priority-tagged 11 frame is vlan-tagged chapter 3 functional operation 107 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information software. alternatively, in external loopback mode, data can be transmitted to and received from the external network. all transmit and receive function programming, such as automatic transmit padding and receive pad stripping, operates the same way in loopback as it does in normal operation. the external loopback through the phy interface bus requires a two-step operation. first the external phy must be placed into a loopback mode. then the network controller must be placed into the external loopback mode by setting exloop (cmd2, bit 3). an external phy with a standard mii can be placed into loopback mode by writing to the phy access register. alternatively for external loopback the phy can be put into full-duplex mode, and an external set of jumpers can be used to connect the network receive path to the transmit path. figure 24 on page 107 shows three possible loopback paths. figure 24. internal and external loopback paths the internal loopback is controlled by inloop (cmd2, bit 4). when set to 1, this bit causes the internal transmit data path to loop back to the internal receive data path. the run bit (cmd0, bit 0) must be cleared to 0 before the state of the inloop bit is changed. the mii management port (mdc, mdio) is unaffected by the inloop bit. the internal mii interface is mapped in the following way: the txd[3:0] nibble data path is looped back onto the rxd[3:0] nibble data path tx_clk and rx_clk are driven by the same internal clock so that no external tx_clk signal is needed. tx_en is looped back as rx_dv. tx_en is ored with the crs pin and is looped back as crs. ? the col input is driven low. network controller internal loopback network controller transmitter receiver phy phy internal loopback external loopback jumper 108 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information tx_er is not driven by the network controller and therefore not looped back. internal loopback should not be used on a live network because transmit data path signals might interfere with network traf?. the phy should be disconnected from the network or put into the ?solate?state before internal loopback is used. 3.10.10 full-duplex operation when the network controller is in full-duplex mode, it can receive a frame from the network at the same time that it is transmitting a frame. full-duplex operation is normally enabled through the auto- negotiation process. alternatively full-duplex operation can be enabled by clearing the en_pmgr bit in cmd3 register to 0 to disable the port manager and then setting the force_full_duplex bit (cmd3, bit 12). in full-duplex mode the network controller behaves the same way it does in half-duplex mode with the following exceptions: transmission is not deferred while receive is active. the ipg counter which governs transmit deferral during the ipg between back-to-back transmits is started when transmit activity for the ?st packet ends, instead of when transmit and carrier activity ends. the collision indication input to the mac engine is ignored. 3.10.11 external phy interface the network controller supports the media independent interface (mii) as de?ed by the ieee 802.3 standard. this reconciliation sublayer interface allows a variety of phys (100base-tx, 100base- fx, 100base-t4, 100base-t2, 10base-t, etc.) to be attached to the mac engine without future upgrade problems. the mii interface is a 4-bit (nibble) wide data path interface that runs at 25 mhz for 100-mbit/s networks or 2.5 mhz for 10-mbit/s networks. the interface consists of two independent data paths, receive (rxd(3:0)) and transmit (txd(3:0)), control signals for each data path (rx_er, rx_dv, tx_en), network status signals (col, crs), clocks (rx_clk, tx_clk) for each data path, and a two-wire management interface (mdc and mdio). see figure 25 on page 109. the transmit and receive paths in the controller's mac are independent. the tx_clk and rx_clk need not run at the same frequency. tx_clk can slow down or stop without affecting receive and vice versa. it is only necessary to respect the minimum clock high and low time speci?ations when switching tx_clk or rx_clk. this facilitates operation with phys that use mii signaling but do not adhere to 802.3 mii speci?ations. 3.10.11.1 mii transmit interface the mii transmit clock is generated by the external phy and is sent to the network controller on the tx_clk input pin. the clock can run at 25 mhz or 2.5 mhz, depending on the speed of the network to which the external phy is attached. the data is a nibble-wide (4 bits) data path, txd(3:0), from chapter 3 functional operation 109 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the network controller to the external phy and is synchronous with the rising edge of tx_clk. the transmit process starts when the network controller asserts tx_en, which indicates to the external phy that the data on txd(3:0) is valid. ieee standard 802.3 provides a mechanism for signalling unrecoverable errors through the mii to the external phy with the tx_er output pin. the external phy responds to this error by generating a tx coding error on the current transmitted frame. the network controller does not use this method of signaling errors on the transmit side. instead, if the network controller detects a transmit error, it inverts the fcs to generate an invalid fcs. since the network controller does not implement the tx_er function, the tx_er pin on the external phy device should be connected to vss. 3.10.11.2 mii receive interface the mii receive clock is also generated by the external phy and is sent to the network controller on the rx_clk input pin. the clock can run at 25 mhz or 2.5 mhz, depending on the speed of the network to which the external phy is attached. figure 25. media independent interface the receive process starts when rx_dv is asserted. rx_dv must remain asserted until the end of the receive frame. if the external phy device detects errors in the currently received frame, it asserts the rx_er signal. rx_er can be used to signal special conditions out of band when rx_dv is not asserted. two de?ed out-of-band conditions for this are the 100base-tx signaling of bad start of frame delimiter and the 100base-t4 indication of illegal code group before the receiver has synchronized with the incoming data. the network controller does not respond to these conditions. all out of band conditions are currently treated as null events. certain in-band non-ieee 802.3- compliant ?w control sequences may cause erratic behavior for the network controller. consult the switch/bridge/router/hub manual to disable the in-band ?w control sequences if they are being used. 4 rxd(3:0) rx_dv rx_er rx_clk 4 txd(3:0) tx_en am79c976 mii interface col crs receive signals transmit signals management port signals network status signals tx_clk mdio mdc network controller 110 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.10.11.3 mii network status interface the mii also provides the crs (carrier sense) and col (collision sense) signals that are required for ieee 802.3 operation. carrier sense is used to detect non-idle activity on the network for the purpose of inter-frame spacing timing in half-duplex mode. collision sense is used to indicate that simultaneous transmission has occurred in a half-duplex network. 3.10.11.4 mii management interface the mii provides a two-wire management interface so that the network controller can control external phy devices and receive status from them. the network controller offers direct hardware support of the external phy device without software intervention. the device automatically uses the mii management interface to read auto-negotiation information from the external phy device and con?ures the mac accordingly. the controller also provides the host cpu indirect access to the external phy through the phy access register. with software support the network controller can support up to 31 external phys attached to the mii management interface. two independent state machines use the mii management interface to poll external phy devices: the network port manager and the auto-poll state machine. the network port manager coordinates the auto-negotiation process, while the auto-poll state machine interrupts the host cpu when it detects changes in user-selected phy registers. the network port manager sends a management frame to the default phy about once every 600 ms to determine auto-negotiation results and the current link status. the network port manager uses the auto-negotiation results to set the mac's speed, duplex mode, and ?w control ability. changes detected by the network port manager affect the operation of the mac and mib counters. for example, if link failure is detected, the transmitter increments the xmtlosscarrier counter each time it attempts to transmit a frame. the auto-poll state machine periodically sends management frames to poll the status register of the default phy device plus up to 5 user-selected phy registers and interrupts the host processor if it detects a change in any of these registers. the auto-poll state machine does not change the state of the mac engine. 3.10.11.5 mii management frames the format of an mii management frame is de?ed in clause 22 of ieee standard 802.3. the start of an mii management frame is a preamble of 32 ones that ensures that all of the external phys are synchronized on the same interface. (see figure 26 on page 111.) loss of synchronization is possible due to the hot-plugging capability of the exposed mii. the preamble can be suppressed as described below if the external phy is designed to accept frames with no preamble. chapter 3 functional operation 111 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 26. frame format at the mii interface connection the preamble (if present) is followed by a start ?ld (st) and an operation ?ld (op). the operation ?ld (op) indicates whether the network controller is initiating a read or write operation. this ?ld is followed by the external phy address (phyad) and the register address (regad). the phy address of 1fh is reserved and should not be used. the register address ?ld is followed by a bus turnaround ?ld. during a read operation, the bus turnaround ?ld is used to determine if the external phy is responding correctly to the read request or not. the network controller ?ats the mdio for both mdc cycles. during the second cycle of a read operation, if the external phy is synchronized to the network controller, the external phy drives a 0. if the external phy does not drive a 0, the network controller signals a mreint (int0, bit 16) interrupt, if mreinten (inten0, bit 16) is set to a 1. this interrupt indicates that the network controller had an mii management frame read error and that the data read is not valid. during a write access the network controller drives a 1 for the ?st bit time of the turnaround ?ld and a 0 for the second bit time. after the turn around ?ld comes the data ?ld. for a write access the network controller ?ls this ?ld with data to be written to the phy device. for a read access the external phy device ?ls this ?ld with data from the selected register. the last ?ld of the mii management frame is an idle ?ld that is necessary to give ample time for drivers to turn off before the next access. mii management frames transmitted through the mdio pin are synchronized with the rising edge of the management data clock (mdc). the network controller drives the mdc to 0 and three-states the mdio any time the mii management port is not active. to help to speed up the reading and writing of the mii management frames to the external phy, the mdc can be sped up to 10 mhz by setting the fmdc bits in ctrl2. the ieee 802.3 speci?ation requires use of the 2.5-mhz clock rate, but 5 mhz and 10 mhz are available for the user. the intended applications are that the 10-mhz clock rate can be used for a single external phy on an adapter card or motherboard. the 5-mhz clock rate can be used for an exposed mii with one external phy attached. the 2.5-mhz clock rate is intended to be used when multiple external phys are connected to the mii management port or if compliance to the ieee 802.3 standard is required. preamble 1111....1111 op 10 rd 01 wr phy address register address ta z0 rd 10 wr data 2 bits 5 bits 5 bits 2 bits 32 bits st 01 2 bits 16 bits 1 bit idle z 112 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.10.11.6 host cpu access to external phy the host cpu can indirectly read and write external phy registers through the phy access register. to write to a phy register the host cpu puts the register data into the phy_data ?ld of the phy access register, speci?s the address of the external phy device in the phy_addr ?ld and the phy register number in the phy_reg_addr ?ld, and sets the phy_wr_cmd bit. to read from a phy register the host cpu speci?s the address of the external phy device in the phy_addr ?ld and the phy register number in the phy_reg_addr ?ld of the phy access register and sets the phy_rd_cmd bit. the host cpu can then poll the register until the phy_cmd_active bit is 0, or it can wait for the mii management command complete interrupt (mccint in the int0 register). when the phy_cmd_active bit is 0, the phy_data ?ld contains the data read from the speci?d external phy register. if an error occurs in the read operation, the phy_rd_err bit in the phy access register and the mii management read error interrupt (mreint) bit in the interrupt0 register are set, and if the corresponding enable bit is set (mreinten in the interrupt enable register), the host cpu is interrupted. the host cpu must not attempt a second phy register access until the ?st access is complete. when the access is complete, the phy_cmd_active bit in the phy access register is cleared and the mii management command complete interrupt (mccint) bit in the interrupt register is set to 1, and if the corresponding enable bit is set, the host cpu is interrupted. the host can either wait for this interrupt, or it can use some other method to ensure that it waits for a long enough time. note that with a 2.5 mhz mdc clock it takes about 27 s to transmit a management frame with a preamble. however, if the auto-poll or port manager state machines are active, there may be a delay in sending a host generated management frame while other frames are sent. under these conditions, the host should always check for command completion. for an mii management frame transmitted as the result of a host cpu access to the phy access register, preamble suppression is controlled by the preamble suppression bit (phy_pre_sup) in the phy access register. if this bit is set to 1 the preamble is suppressed. otherwise, the frame includes a preamble. the host cpu should only set the preamble suppression bit when accessing a register in a phy device that is known to be able to accept management frames without preambles. for phy devices that comply with clause 22 of ieee standard 802.3, bit 6 of phy register 1 is xed at 1 if the phy accepts management frames with the preamble suppressed. 3.10.11.7 auto-poll state machine as de?ed in the ieee 802.3 standard, the external phy attached to the network controller s mii has no way of communicating important timely status information back to the network controller. unless it polls the external phy s status register, the network controller has no way of knowing that an external phy has undergone a change in status. although it is possible for the host cpu to poll registers in external phy devices, the network controller simpli?s this process by implementing an automatic polling function that periodically polls up to 6 user-selected phy registers and interrupts the host cpu if the contents of any of these registers change. chapter 3 functional operation 113 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the automatic polling of phy registers is controlled by six 16-bit auto-poll registers, autopoll0 to autopoll5 shown in figure 27. by writing to the auto-poll registers, the user can independently de?e the phy addresses and register numbers for six external phy registers. the registers are not restricted to a single phy device. in the auto-poll registers there is an enable bit for each of the selected phy registers. when the host cpu sets the apep bit to enable auto-polling, the auto-poll logic reads the phy register corresponding to each enabled auto-poll register and stores the result in the corresponding auto-poll data register. (there is one auto-poll data register for each of the six phy registers.) thereafter, at each polling interval, the auto-poll logic compares the current contents of the selected phy register with the corresponding auto-poll data register. if it detects a change, it sets the mii management auto-poll interrupt (apint) in the interrupt register, which causes an interrupt to the host cpu (if that interrupt is enabled). figure 27. auto-poll and auto-poll data registers when the contents of one of the selected phy registers changes, the corresponding auto-poll data register is updated so that another interrupt can occur when the data changes again. the auto-poll data registers are accessed indirectly through the ap_value register as shown in figure 28. the host cpu ?st writes the number (0-5) of the desired auto-poll data register to the ap_val_addr ?ld and sets the ap_val_rd_cmd bit to 1. setting ap_val_rd_cmd to 1 starts the read cycle and automatically sets the ap_cmd_active bit. the host cpu then polls the ap_cmd_active bit until this bit is 0. at this time the ap_val ?ld of the ap_value register contains the contents of the selected auto-poll data register. the host cpu must not write to the ap_value register while the ap_cmd_active bit has the value 1. external 0 1 31 auto_poll_data[5:0] 0 1 4 5 adr phy adr phy adr phy adr phy adr phy adr phy auto_poll[5:0] 0 1 4 5 phyn 114 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information figure 28. indirect access to auto-poll data registers auto-poll register 0 differs from the other auto-poll registers in several ways. the phy address (ap_phy0_addr) ?ld of this register de?es the default phy address that is used by both the auto-poll state machine and the network port manager. the register number ?ld is ?ed at 1 (which corresponds to the external phy status register), and the register is always enabled. this means that if the auto-poll state machine is enabled, it always polls register 1 of the default phy and interrupts the host cpu when it detects a change in that register. in addition to the phy address, register number, and enable bit, the auto-poll registers contain two other control bits for each of the 5 user-selected registers. these bits are the preamble suppression (ap_pre_sup) and default phy (ap_dflt_phy) bits. if the preamble suppression bit is set, the auto-poll sends management frames to the corresponding register with no preamble ?ld. the host cpu should only set the preamble suppression bit for registers in phy devices that are known to be able to accept management frames without preambles. for phy devices that comply with clause 22 of ieee standard 802.3, bit 6 of phy register 1 is xed at 1 if the phy accepts management frames with the preamble suppressed. if the default phy bit (ap_phyx_dflt) is set, the corresponding preamble suppression bit and phy address ?ld are ignored. in this case the auto-poll state machine uses the default phy address from the ap_phy0_addr ?ld, and suppresses the preamble if the network port manager logic has determined that the default phy device accepts management frames with no preamble. if the network port manager logic has not determined that the default phy device accepts management frames with no preamble, the auto-poll state machine does not suppress the preamble when accessing the selected register. the auto-poll state machine is enabled when the auto-poll external phy (apep) bit (cmd3, bit 10) is set to 1. if apep is cleared to 0, the auto-poll machine does not poll any phy registers regardless of the state of the enable bits in the auto-poll registers. the apep bit has no effect on the network port manager, which may poll the default phy even when the state of the apep bit is 0. the host cpu must ensure that the apep bit is cleared to 0 before it changes the contents of any of the auto-poll registers. auto_poll_data[5:0] 0 1 4 5 adr value ap_value register chapter 3 functional operation 115 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the auto-poll s frequency of generating mii management frames can be adjusted by setting of the apdw bits (ctrl2, bits 2-0). 3.10.12 network port manager the network controller does not require software intervention to control and con?ure an external phy attached to the mii. the controller contains an automatic con?uration system called the network port manager. the network port manager initiates auto-negotiation in the external phy when necessary and monitors the results. when auto-negotiation is complete, the network port manager sets up the mac to be consistent with the negotiated con?uration. the network port manager auto-negotiation sequence requires that the external phy respond to the auto-negotiation request within 7.5 seconds. otherwise, system software is required to properly control and con?ure the external phy attached to the mii. after auto negotiation is complete, the network port manager generates mii management frames about once every 600 ms to monitor the status of the external phy. the network port manager is enabled when the enable port manager (en_pmgr) bit (cmd3, bit 14) is set to 1. although the network port manager and the auto-poll state machine both poll the external phy, the two modules have different functions. the port manager manages auto-negotiation, while the auto- poll state machine monitors user-selected external phy registers. 3.10.13 auto-negotiation support the external phy and its link partner may have one or more of the following capabilities: 100base- t4, 100base-tx full-/half-duplex, 10base-t full-/half-duplex, and mac control pause frame processing. during the auto-negotiation process the two phy devices exchange information about their capabilities and then select the best mode of operation that is common to both devices. the modes of operation are prioritized according to the order shown in table 31 on page 115 (with the highest priority shown at the top of the table). auto-negotiation goes further by providing a message-based communication scheme called, next pages, before connecting to the link partner. the network port manager does not support this feature. however, the host cpu can disable the network port manager and manage next pages by accessing the phy device through the phy access register. the host cpu can disable the network port manager by clearing the enable port manager (en_pmgr) bit (cmd3, bit 14) to 0. table 31. auto-negotiation capabilities network speed physical network type 200 mbit/s 100base-x, full duplex 100 mbit/s 100base-t4, half duplex 100 mbit/s 100base-x, half duplex 20 mbit/s 10base-t, full duplex 10 mbit/s 10base-t, half duplex 116functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information to control the auto-negotiation process, the network port manager generates mii management frames to execute the procedure described below. the network port manager is held in the idle state while h_reset is asserted and while the en_pmgr bit is cleared. when none of these conditions are true, the network port manager proceeds through the following steps: 1. if xphyrst is set, write to the phy's control register (r0) to set the soft reset bit and cause the phy to reset. the network port manager then periodically reads the phy's control register (r0) until the reset is complete. 2. if xphyrst is not set or after the phy reset is complete, the phy's status register (r1) is read. 3. if the phy's auto-negotiation ability bit (r1, bit 3) is 0 or if the xphyane bit in the control2 register is 0 and if this is the ?st pass through this procedure since en_pmgr was set to 1, write to the phy's control register (r0) to disable auto-negotiation and set the speed and duplex mode to the values speci?d by the xphysp and xphyfd bits in the control2 register anded with the appropriate bits from the phy's technology ability field. then proceed to step 8. 4. if this is the ?st pass through this procedure since en_pmgr was set to 1, write to the auto- negotiation advertisement register (r4). bits a0 to a4 of the technology ability ?ld of r4 are taken from bits 15 to 11 in r1. (the technology ability ?ld of r4 consists of bits 5 through 12, where bit 5 of r4 corresponds to technology ability bit a0.) bit a5 of the technology ability ?ld indicates the mac's ability to respond to mac control pause frames. this bit is set equal to the value of the negotiate pause ability (npa) bit in the flow control register. bit a6 indicates asymmetric pause operation for full-duplex links. this bit is copied from the negotiate asymmetric pause ability (napa) bit in the flow control register. the next page, acknowledge, and remote fault bits are cleared to 0, and the selector field is set to 00001 to indicate ieee standard 802.3. 5. if this is the ?st pass through this procedure since en_pmgr was set to 1, write to the control register (r0) to restart auto-negotiation. 6. poll r1 at 1.9 second intervals until the auto-negotiation complete bit is set to 1. if auto- negotiation is not complete after four polling intervals, go back to step 1. 7. read the auto-negotiation link partner ability register (r5). set the mac's speed, duplex mode, and pause ability to the highest priority mode that is common to both phy devices. 8. poll r1 at 600 ms intervals until the link status bit is 1. if link status is not found to be 1 after four polling intervals, go back to step 1. 9. poll r1 at intervals of about 600 ms until the link status bit is 0. go to step 1. table 32. sources of auto-negotiation advertisement register (r4) bits bits 1000base-t function source of data 4.15 next page r6.2 4.14 reserved cleared to 0 chapter 3 functional operation 117 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information note: the notation rx.y stands for phy management register x, bit y. when auto-negotiation is complete, the network port manager examines the mf preamble suppression bit in phy register 1. if this bit is set, the network port manager suppresses preambles on all frames that it sends until one of the following events occurs: ? a hardware reset occurs. ? the en_pmgr bit (cmd3 register, bit 14) is cleared. ? a management frame read error occurs. ? the external phy is disconnected. the network port manager is not disabled when the mdio pin is held low when the mii management interface is idle. if no phy is connected and an external pull-down resistor is attached, reads of the external phy's registers return all zeros, and no read error is reported. if a phy is disconnected, causing mdio to go low, an miipd interrupt occurs. 3.10.13.1 auto-negotiation with multiple phy devices the mii management interface (mdc and mdio) can be used to manage more than one external phy device. the external phy devices may or may not be connected to the network controller s mii bus. for example, two phy devices can be connected to the network controller s mii bus so that the mac can communicate over either a twisted-pair cable or a ?er-optic link. conversely, several network controllers may share a single integrated circuit that contains several phy devices with separate mii buses but with only one mii management bus. in this case, the mii management interface of one network controller could be used to manage phy devices connected to different network controllers. if more than one phy device is connected to the mii bus, only one phy device is allowed to be enabled at any one time. since the network port manager can not detect the presence of more than one phy on the mii bus, the host cpu is responsible for making sure that only one phy is enabled. the host cpu can use the phy access register to set the isolate bit in the control register (register 0, bit 10) of any phy that needs to be disabled. 4.13 remote fault cleared to 0 4.12 reserved cleared to 0 4.11 asm_dir napa 4.10 pause npa 4.9 100base-t4 r1.15 4.8 100base-tx, full duplex r1.14 4.7 100base-tx r1.13 4.6 10base-t, full duplex r1.12 4.5 10base-t r1.11 4.4:0 selector field 00001b table 32. sources of auto-negotiation advertisement register (r4) bits 118 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.10.13.2 operation without mii management interface the port manager normally sets up the speed, duplex mode, and ?w control (pause) ability of the mac based on the results of auto-negotiation. however, it is possible to operate the device with no mii management interface connection, in which case the port manager is not able to start the auto- negotiation process or set up the mac based on auto-negotiation results. this may happen if the network controller is connected to a multi-phy device that has only one mii management interface that is shared among several phys. if the network controller is operating without a mii management interface connection to its external phy, the host cpu can force the mac into the desired state by clearing the en_pmgr bit in cmd3 register to 0 to disable the port manager, then writing to the following bits: 1. force_full_duplex (cmd3, bit 12) 2. force_link_status (cmd3, bit 11) 3. force receive pause enable (frpe, flow_control, bit 21) 4. force transmit pause enable (ftpe, flow_control, bit 22) these bits set up the duplex mode, link status, and ?w control ability in the mac and put the mac into the link pass state. 3.10.14 regulating network traf? the network controller provides two hardware mechanisms for regulating network traf?: 802.3x flow control and collision-based back pressure. 802.3x flow control applies to full-duplex operation only, while back pressure applies to half-duplex operation only. 802.3x flow control works by sending and receiving mac control pause frames, which cause the receiving station to postpone transmissions for a time determined by the contents of the pause frame. back pressure forces collisions to occur when other nodes attempt to transmit, thereby preventing other nodes from transmitting for periods of times determined by the back-off algorithm. the device includes support for two styles of full-duplex ?w control, fixed length pause ?w control and variable length pause ?w control. in the variable length pause style, which is similar to an xon-xoff protocol, a pause frame whose request_operand ?ld (bytes 17 and 18) contains 0ffffh is sent to prevent the link partner from transmitting. later, a pause frame whose request_operand ?ld contains 0 is sent to allow the link partner to resume transmissions. the variable length pause style of ?w control is selected by clearing the fixed length pause bit (fixp, flow control register, bit 18) to 0. for the fixed length pause style of ?w control, a single pause frame is sent to halt transmissions for a predetermined period of time. the contents of the request_operand ?ld of this frame are taken from the pause length register. this style of ?w control is selected by setting the fixed length pause bit (fixp) to 1. chapter 3 functional operation 119 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 3.10.14.1 mac control pause frames the format of a mac control pause frame is shown in table 33. when a network station that supports ieee 802.3x flow control receives a pause frame, it must suspend transmissions after the end of any frame that was being transmitted when the pause frame arrived. the length of time for which the station must suspend transmissions is given in the request_operand ?ld of the pause frame. this pause time is given in units of pause_quanta, where, one pause_quantum is 512 bit times. the request_operand ?ld is interpreted as big-endian data octet 17 is the most signi?ant byte and octet 18 is the least signi?ant byte. 3.10.14.2 back pressure the network controller supports collision-based back pressure for congestion control when the device is operating in half-duplex mode. when the mac begins receiving a frame that passes the address matching criteria and if back pressure is enabled, the mac intentionally causes a collision by transmitting a ?hantom?frame. this phantom frame consists of a normal 7-byte preamble and 1-byte sfd followed by 63 bytes of alternating 1 and 0 bits. this frame should be interpreted as a runt frame with fcs error by any standard receiver. back pressure does not affect the transmission of a frame. the mac only forces a collision when it begins to receive a new frame. back pressure is enabled when the bkprs_en bit in cmd3 is set, the device is operating in half- duplex mode, and the receiver is congested. receiver congestion is de?ed in the next section. the bkprs_en bit allows the software to separate the decision about whether or not to apply back pressure from the decision about when to apply back pressure. if the bkprs_en bit is set, back pressure is applied when the device is operating in half-duplex mode and the receiver is congested. if the bkprs_en bit is 0, back pressure is never applied. the generation of a back-pressure collision causes the xmtbackpressure mib counter to increment. table 33. mac control pause frame format octet numbers field name value 1-6 destination address 01-80-c2-00-00-01 7-12 source address sender s physical address 13-14 length/type 88-08 15-16 mac control opcode 00-01 17-18 request_operand pause time measured in pause_quanta, which are equal to 512 bit times 19-60 pad zeros 61-64 fcs fcs 120 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.10.14.3 enabling traf? regulation mac control pause frame generation or half-duplex back pressure assertion is controlled by the host cpu when it sets or clears the flow control command (fccmd) bit. when the fccmd bit is set, the receiver is considered to be in the ?ongested state. when the fccmd bit is cleared, the receiver is not considered to be congested. if the controller is in the half-duplex mode and the bkprs_en bit is set, back pressure is asserted as long as the receiver is in the congested state. if the controller is in the full-duplex mode, a mac control pause frame is automatically transmitted when the receiver enters the congested state, and optionally a second pause frame is transmitted when the receiver leaves the congested state. in half- duplex mode the network controller does not respond to received pause frames. when the device is operating in full-duplex mode, the content of the pause frames and the number of pause frames transmitted are controlled by the fixed length pause control bit (fixp). when fixp is set to 1, a single pause frame is transmitted when the receiver enters the congested state. the contents of the request_operand ?ld of the pause frame are taken from the pause length ?ld of the flow control register (pause_len). this frame causes the link partner to halt transmissions for a predetermined length of time that corresponds to the value read from the pause_len ?ld. if fixp is 0, when the receiver enters the congested state, a pause frame is transmitted with the request_operand ?ld set to ffffh, so that the link partner stops transmitting for a very long time. when the receiver exits the congested state, a second pause frame is transmitted with the request_operand ?ld cleared to 0000h, so that the link partner resumes transmissions immediately. traf? regulation is affected by the following: ? duplex mode ? flow control command (fccmd) bit ? fixed length pause (fixp) bit ? 16-bit pause length ?eld (pause_len) ? negotiate pause ability (npa) bit ? negotiate asymmetric pause ability (napa) bit ? force receive pause enable (frpe) bit ? force transmit pause enable (ftpe) bit 3.10.14.4 software control of traf? regulation the host cpu uses the flow control command bit (fccmd) to cause the controller to transmit ?w control frames automatically or to enable back pressure. in half-duplex mode, back pressure is enabled when fccmd is set to 1, and it is disabled when fccmd is cleared to 0. in full-duplex mode, the act of setting fccmd to 1 causes a pause frame to be sent. the contents of the request_operand ?ld of the frame depend on the state of the fixp bit. if fixp is 1, the contents chapter 3 functional operation 121 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information of the request_operand ?ld are copied from the pause_len ?ld of the flow control register. if fixp is 0, the contents of the request_operand ?ld are set to 0ffffh. in full-duplex mode, if fixp is 0, the act of clearing fccmd to 0 causes a pause frame to be sent with its request_operand ?ld cleared to 0. if fixp is set to 1, the fccmd bit is self-clearing?he cpu does not have to write to the network controller to clear the fccmd bit. this allows the cpu to use a single write access to cause a pause frame to be sent with a predetermined request_operand ?ld. the effects of the fccmd bit are summarized in table 34. 3.10.14.5 programming the pause length before the host cpu changes the contents of the pause length ?ld of the flow control register, it must make sure that a suf?ient amount of time (about 50 s) has elapsed since the last time the register was updated. when the host cpu changes the value of this ?ld it must also write a 1 to the pause_len_chg bit (flow_control, bit 30). this bit is used internally to synchronize the change in pause length value with the transmission of ?w control frames. the bit is automatically cleared to 0 after the update process has ?ished. after the internal logic has cleared this bit, it is safe to write a new value to the pause length ?ld. 3.10.14.6 enabling receive pause the ability to respond to received pause frames, or receive pause ability, is controlled independently from the transmission of pause frames. when receive pause ability is enabled, the receipt of a pause frame causes the device to stop transmitting for a time period that is determined by the contents of the pause frame. receive pause ability is enabled either by auto-negotiation or by the force receive pause enable bit (frpe, flow_control, bit 21). if the frpe bit is set, receive pause ability is enabled regardless of the results of auto-negotiation. if frpe is not set, the pause ability is determined by auto- negotiation. clause 37 of ieee standard 802.3, 1998 edition de?es two types of pause con?urations, symmetric pause and asymmetric pause. in a symmetric con?uration both link partners transmit and receive table 34. fccmd bit functions fccmd transition fixp duplex mode action 0 to 1 x half enable back pressure 1 to 0 x half disable back pressure 0 to 1 1 full send pause frame with request operand equal to the contents of the pause length register. automatically clear fccmd to 0. 1 to 0 1 full no action. (fccmd is cleared automatically when fixp = 1.) 0 to 1 0 full send pause frame with request operand equal to 0ffffh. 1 to 0 0 full send pause frame with request operand equal to 0000h. 122 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information pause frames. in an asymmetric con?uration only one link partner transmits pause frames and the other one receives them. during the auto-negotiation process each link partner indicates its con?uration preference in the form of pause and asm_dir bits that are sent in mii management frames. the encoding of these bits is shown in table 35. during the auto-negotiation process the phy device attached to the lan ethernet controller controller exchanges con?uration information with the phy device on the other end of the network link segment as described in ieee standard 802.3, 1998 edition, clause 28. the value of the pause bit that is sent in mii management frames is copied from the negotiate pause ability bit (npa, flow_control register, bit 19), and the value of the asm_dir bit is copied from the negotiate asymmetric pause ability bit (napa, flow_control register, bit 20). after auto-negotiation has ?ished, receive pause is enabled if either 1. the npa bit is set and link partner s pause bit is also set or 2. the npa and napa bits are both set and the link partner s asm_dir bit is set. after auto-negotiation has ?ished, transmit pause is enabled if either 1. the npa bit is set and link partner s pause bit is also set or 2. the napa bit is set and the link partner s pause and asm_dir bits are set. 3.10.14.7 pause frame reception a mac control pause frame is any valid frame with the following: a destination address ?ld value equal to the mac s physical address or equal to the reserved multicast address 01-80-c2-00-00-01, a length/type ?ld value equal to 88-08, and a mac control opcode ?ld value equal to 0001. if such a frame is received while pause ability is enabled, the mac device waits until the end of the frame currently being transmitted (if any) and then stops transmitting for a time equal to the value of the request_operand ?ld (octets 17 and 18) multiplied by 512-bit times. if another mac control pause frame is received before the pause timer has timed out, the pause timer is reloaded from the request_operand ?ld of the new frame so that the new frame overrides the earlier one. table 35. pause encoding pause asm_dir capability 0 0 no pause 0 1 asymmetric pause toward link partner 1 0 symmetric pause 1 1 both symmetric pause and asymmetric pause toward local device chapter 3 functional operation 123 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information received mac control pause frames are handled completely by the hardware. they are not passed on to the host computer. however, mac control frames with opcodes not equal to 0001h are treated as normal frames, except that their reception causes the unsupported opcodes counter to be incremented. since the host computer does not receive mac control pause frames, 32-bit mib counters have been added to record the following: mac control frames received unsupported opcodes received pause frames received 3.10.15 delayed interrupts to reduce the host cpu interrupt service overhead the network controller can be programmed to postpone the interrupt to the host cpu until either a programmable number of receive or transmit interrupt events have occurred or a programmable amount of time has elapsed since the ?st interrupt event occurred. the use of the delayed interrupt registers allows the interrupt service routine to process several events at one time without having to return control back to the operating system between events. a receive interrupt event occurs when receive interrupts are enabled, and the network controller has completed the reception of a frame and has updated the frame's descriptors. a receive interrupt event causes the receive interrupt (rint0) bit in the int0 register to be set if it is not already set. similarly a transmit interrupt event occurs when transmit interrupts are enabled, and the network controller has copied a transmit frame's data to the transmit fifo and has updated the frame's descriptors. a transmit interrupt event causes the appropriate transmit interrupt (tintx) bit in the int0 register to be set if it is not already set. note that frame receptions or transmissions affect the interrupt event counter only when the corresponding receive or transmit interrupts are enabled. the network controller contains two delayed interrupt registers that can be programmed to delay two groups of interrupts. corresponding to each delayed interrupt register is an interrupt group register that selects which interrupt events are included in each group. each interrupt group register has ve include bits, dly_int_x_t[3:0] and dly_int_x_r0, that correspond to transmit interrupts (tint[3:0]) for each of 4 priority levels and the receive interrupt. the x in dly_int_x stands for a for group a interrupts and for b in group b interrupts. for each include bit that is set in a particular interrupt group register, the corresponding interrupt event is included in the interrupt group. any interrupt event that is included in an interrupt group is delayed until the conditions programmed into the corresponding delayed interrupt register are met. each delayed interrupt register contains a 5-bit event count ?ld and a 11-bit maximum delay time ?ld. each time the host cpu clears a rint or tint bit that corresponds to an interrupt event that is included in an interrupt group, the contents of the event count ?ld of the corresponding delayed interrupt register are loaded into an internal interrupt event counter, the contents of the maximum 124 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information delay time ?ld are loaded into an internal interrupt event timer, and the interrupt event timer is disabled. each time a receive or transmit interrupt event that is included in that group occurs, the interrupt event counter is decremented by 1 and the interrupt event timer is enabled, or if it has already been enabled, it continues to count down. once the interrupt event timer has been enabled, it decrements by 1 every 10 microseconds. when either the interrupt event counter or the interrupt event timer reaches zero, the pirqa_l pin is asserted. 3.10.16 power management support the network controller supports power management as de?ed in the pci bus power management interface speci?ation v1.1 and network device class power management reference speci?ation v1.0. these speci?ations de?e the network device power states, pci power management interface including the capabilities data structure and power management registers block de?itions, power management events, and onnow network wake-up events. the general scheme for the network controller power management is that when a wake-up event is detected, a signal (pme_l) is generated to cause hardware external to the network controller to put the computer into the working (s0) mode. the controller supports three types of wake-up events: magic packet frame detect link state change pattern match detect all three wake-up events can cause wake-up from any power state including d3 cold (pci bus power off and clock stopped). 3.10.16.1 onnow wake-up sequence the system software enables the pme_l signal by setting the pme_en bit in the pmcsr register (pci con?uration registers, offset 44h, bit 8) to 1. when a wake-up event is detected, the network controller sets the pme_status bit in the pmcsr register (pci con?uration registers, offset 44h, bit 15). setting this bit causes the pme_l signal to be asserted. assertion of the pme_l signal causes external hardware to wake up the cpu. the system software then reads the pmcsr register of every pci device in the system to determine which device asserted the pme_l signal. when the software determines that the signal came from the network controller, it writes to the device's pmcsr to put the device into power state d0. the software then writes a 1 to the pme_status bit to clear the bit and turn off the pme_l signal, and it calls the device's software driver to tell it that the device is now in state d0. the system software can clear the pme_status bit either before, after, or at the same time that it puts the device back into the d0 state. chapter 3 functional operation 125 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the type of wake-up is con?ured by software using the bits lcmode_sw, pmat_mode, and mpen_sw in the cmd7 register. these bits are only reset by the power-on reset (por) so that they maintain their values across pci bus resets. 3.10.16.2 link change detect link change detect is one of the wake-up events that is de?ed by the onnow speci?ation. link change detect mode is set when the lcmode_sw bit (cmd7, bit 0) is set. when this bit is set, any change in the link status causes the lc_det bit (stat0, bit 10) to be set. when the lc_det bit is set, the pme_status bit (pmcsr register, bit 15) is set. if the pme_en bit (pmcsr, bit 8)is set, then the pme_l signal is also asserted. 3.10.16.3 magic packet technology mode a magic packet frame is a frame that is addressed to the network controller and contains a data sequence made up of 16 consecutive copies of the device's physical address (padr[47:0]) anywhere in its data ?ld. the frame must also cause an address match. by default, it must be a physical address match, but if the mpplba bit (cmd3, bit 9) is set, logical and broadcast address matches are also accepted. regardless of the setting of mpplba, the sequence in the data ?ld of the frame must be 16 repetitions of the device's physical address (padr[47:0]). magic packet technology mode is enabled by setting the mpen_sw bit (cmd7, bit 1). if the run bit is set, the rx_spnd bit must also be set to disable the normal receive mode. magic packet technology mode is disabled by clearing the enable bit. when the network controller detects a magic packet frame, it sets the mp_det bit (stat0, bit 11), the mpint bit (int0, bit 13), and the pme_status bit (pmcsr, bit 15). if the pme_en bit is set, the pme_l signal is asserted as well. if intren (cmd0, bit 1) and mpinten (inten0, bit 13) are set to 1, pirqa_l is asserted. the pci bus interface clock (pci_clk) is not required to be running while the device is operating in magic packet technology mode. either of the pirqa_l, or the pme_l signal may be used to indicate the receipt of a magic packet frame when the clk is stopped. 3.10.16.3.1 onnow pattern match mode in the onnow pattern match mode, the network controller compares the incoming packets with up to eight patterns stored in the pattern match ram (pmr). the stored patterns can be compared with part or all of incoming packets, depending on the pattern length and the way the pmr is programmed. when a pattern match has been detected, the pmat_det bit (stat0, bit 12) is set. this causes the pme_status bit (pmcsr, bit 15) to be set, which in turn asserts the pme_l signal if the pme_en bit (pmcsr, bit 8) is set. pattern match mode is enabled by setting the pmat_mode bit (cmd7,bit 3). the run bit (cmd0, bit 0) and either the rx_spnd bit (cmd0, bit 3) or the rx_fast_spnd bit (cmd0, bit 5) must also be set before pmat_mode is set. 126functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information the run or suspend bits must not be reset while pattern match mode is enabled. the controller can be programmed to save the wake-up frame so that the software can respond to the frame that caused the cpu to wake up. this feature is enabled by setting the pmat_save_match bit (cmd7, bit 4) together with the pmat_mode bit. the following procedure can be used to enter pattern match mode with pmat_save_match enabled: 1. set tx_spnd and either rx_spnd or rx_fast_spnd. 2. wait until rx_suspended and tx_suspended are set. 3. clear run. 4. set rx_spnd, tx_spnd, and run. 5. set pmat_mode and pmat_save_match. when the cpu wakes up, it can use the following procedure to restart the controller and retrieve the wake-up frame. 1. read stat0 to determine what caused the wake-up. 2. clear pmat_mode. 3. if wake-up was caused by a pattern match, set up a receive descriptor for the wake-up frame. 4. clear rx_spnd and tx_spnd. 5. set rdmd0. 3.10.16.3.2 pattern match ram (pmr) the pmr is organized as an array of 64 words by 40 bits as shown in figure 29. the pmr is programmed indirectly through the pmat0 and pmat1 registers. pattern match mode must be disabled (pmat_mode bit cleared) to allow reading or writing the pmr. to write a 40-bit word to the pmr the host cpu executes the following steps: 1. write bits 31:0 of the data to pmat1. 2. write to pmat0. set the pmr_wr_cmd bit. put pmr data bits 39:32 into the pmr_b4 ?ld. put the address to be accessed into the pmr_addr ?ld. the sequence for reading a 40-bit word from the pmr is shown below: 1. write to pmat0. set the pmr_rd_cmd bit. put the address to be accessed into the pmr_addr ?ld. 2. read pmat0. the pmr_b4 ?ld contains the high-order byte of data that was read from the pmr. 3. read data bits 31:0 from pmat1. chapter 3 functional operation 127 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the ?st two 40-bit words in the pmr serve as pointers and contain enable bits for the eight possible match patterns. the format of the ?st two words is shown in table 36 on page 127. the remainder of the ram contains the match patterns and associated match pattern control bits. the format of words 2-63 is shown in table 37. table 36. format of pmr pointer words word bits description 0 0 pattern 0 enable. when this bit is 1, pattern 0 is compared with incoming data. when this bit is 0, pattern 0 is ignored. 1 pattern 1 enable. when this bit is 1, pattern 1 is compared with incoming data. when this bit is 0, pattern 1 is ignored. 2 pattern 2 enable. when this bit is 1, pattern 2 is compared with incoming data. when this bit is 0, pattern 2 is ignored. 3 pattern 3 enable. when this bit is 1, pattern 3 is compared with incoming data. when this bit is 0, pattern 3 is ignored. 4-7 reserved. this eld is ignored. 8-15 pattern 0 pointer. this eld contains the pmr address of the rst word of pattern 0. 16-23 pattern 1 pointer. this eld contains the pmr address of the rst word of pattern 1. 24-31 pattern 2 pointer. this eld contains the pmr address of the rst word of pattern 2. 32-39 pattern 3 pointer. this eld contains the pmr address of the rst word of pattern 3. 1 0 pattern 4 enable. when this bit is 1, pattern 4 is compared with incoming data. when this bit is 0, pattern 4 is ignored. 1 pattern 5 enable. when this bit is 1, pattern 5 is compared with incoming data. when this bit is 0, pattern 5 is ignored. 2 pattern 6 enable. when this bit is 1, pattern 6 is compared with incoming data. when this bit is 0, pattern 6 is ignored. 3 pattern 7 enable. when this bit is 1, pattern 7 is compared with incoming data. when this bit is 0, pattern 7 is ignored. 4-7 reserved. this eld is ignored. 8-15 pattern 4 pointer. this eld contains the pmr address of the rst word of pattern 4. 16-23 pattern 5 pointer. this eld contains the pmr address of the rst word of pattern 5. 24-31 pattern 6 pointer. this eld contains the pmr address of the rst word of pattern 6. 32-39 pattern 7 pointer. this eld contains the pmr address of the rst word of pattern 7. table 37. format of pmr data words bits description 0-3 mask. this bit mask determines which of the 4 bytes in this word are compared with frame data. bits 0 to 3 correspond to bytes 1 to 4, respectively. a 1 in a bit position means that the corresponding byte is compared with frame data. a 0 in a bit position means that the corresponding byte is ignored in the comparison. for example, if the value of the mask eld is 5, bytes 1 and 3 are compared with frame data and bytes 2 and 4 are ignored. 128 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information the contents of the pmr are not affected by any reset. the contents are unde?ed after a power-up reset (por). future amd ethernet controllers may contain two pattern match rams, one for patterns 0-3 and one for patterns 4-7. to anticipate compatibility with these controllers, it is recommended that the software follow these rules. 1. word 0 should be written with the pmr_bank bit (pmat0, bit 28) cleared to 0. (in this controller the pmr_bank bit has no effect, but in other controllers it selects one of two pattern match rams.) word 1 should be written with pmr_bank set to 1. 2. data for patterns 0-3 should be written with pmr_bank cleared to 0; data for patterns 4-7 should be written with pmr_bank set to 1. figure 29 on page 129 shows the layout of the data in the pattern match ram. 4-6 skip. the value of the skip eld indicates the number of doublewords of frame data that are skipped before the pattern in this pmr word is compared with data from the incoming frame. a maximum of seven doublewords may be skipped. 7 end of pattern (eop). if this bit is set to 1, this word contains the last byte of the pattern. 8-39 pattern data. the order is such that if bits 8-15 correspond to byte n of the frame, then bits 32-39 correspond to byte n+3. table 37. format of pmr data words bits description chapter 3 functional operation 129 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 29. pattern match ram 3.10.16.3.3 sample pmr patterns the microsoft?and amd device class power management reference speci?ation for the network device class describes ve sample wake-up patterns. the ?st three of these are shown below. arp to machine address 157.55.199.72: table 38. arp packet example offset (decimal) pattern (hex) comments 12 0806 protocol type (0806 = arp) 21 01 arp opcode (01 = request) 38 9d37c748 ip address requested (157.55.199.72) pmr_b4 pmr_b3 pmr_b2 pmr_b1 pmr_b0 pattern match ram address pattern match ram bit number 39 32 31 24 23 16 15 8 7 0 comments 0 p3 pointer p2 pointer p1 pointer p0 pointer pattern enable bits 0-3 first address 1 p7 pointer p6 pointer p5 pointer p4 pointer pattern enable bits 4-7 second address 2 data byte 3 data byte 2 data byte1 data byte 0 pattern control start pattern p 1 2+n data byte 4n+3 date byte 4n+2 data byte 4n+1 data byte 4n+0 pattern control end pattern p 1 j data byte 3 data byte 2 data byte 1 data byte 0 pattern control start pattern p k 7 6 5 4 3 2 1 0 eop skip mask 130 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information directed ip packet (note that this excludes any other directed packets to our mac address): nbt name query/registration for computer name <00>, <03>, <20>: the table below shows how these 3 patterns could be stored in the pattern ram. in this example the third pattern was arbitrarily stored as pattern number 4, and its data was arbitrarily placed in the locations starting at pmr word 40. note that in the 4 columns containing the frame data, the byte in the leftmost column is closer to the start of the frame than the byte in the rightmost column, while the ram data is shown with the most signi?ant byte on the left. table 39. directed ip packet example offset (decimal) pattern (hex) comments 0 08003e304770 destination mac address (station address) 12 0800 protocol type (0800 = ip) 30 9d37c748 ip address (157.55.199.72) table 40. nbt name query/registration example offset (decimal) pattern (hex) comments 12 0800 protocol type (0800 = ip) 23 11 protocol (11= udp) 34 00890089 port number (netbiois name service) 45 10 netbios flags (10 = query or registration) 54 20 name scope null (limited to 32 bytes) 55 46 48 45 42 45 4c 45 46 46 43 43 41 43 41 43 41 43 41 43 41 43 41 43 41 43 41 43 41 43 41 computer name coded in half-ascii ( waker ) table 41. pmr programming example frame offset offset + 0 offset + 1 offset + 2 offset + 3 eop skip mask pmr addr pmr data (hex) 0 00 00 06 02 03 1 00 00 00 28 01 0xxxxxxxx 4xxxxxxxx 8xxxxxxxx 12 08 06 xx xx 0 3 0011 2 xx xx 06 08 33 16 xx xx xx xx 20 xx 01 xx xx 0 1 0010 3 xx xx 01 xx 12 24 xx xx xx xx 28 xx xx xx xx chapter 3 functional operation 131 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 3.10.17 reset there are four different types of reset operations that may be performed on the network controller, h_reset, s_reset, power-up reset, and external phy reset. the following is a description of each type of reset operation. 32 xx xx xx xx 36 xx xx 9d 37 0 3 1100 4 37 9d xx xx 3c 40 c7 48 xx xx 1 0 0011 5 xx xx 48 c7 83 0 08 00 3e 30 0 0 1111 6 30 3e 00 08 0f 4 47 70 xx xx 0 0 0011 7 xx xx 70 47 03 8xxxxxxxx 12 08 00 xx xx 0 1 0011 8 xx xx 00 08 13 16 xx xx xx xx 20 xx xx xx xx 24 xx xx xx xx 28 xx xx 9d 37 0 3 1100 9 37 9d xx xx 3c 32 c7 48 xx xx 1 0 0011 10 xx xx 48 c7 83 0xxxxxxxx 4xxxxxxxx 8xxxxxxxx 12 08 00 xx xx 0 3 0011 40 xx xx 06 08 33 16 xx xx xx xx 20 xx xx xx 11 0 1 1000 41 11 xx xx xx 18 24 xx xx xx xx 28 xx xx xx xx 32 xx xx 00 89 0 2 1100 42 89 00 xx xx 2c 36 00 89 xx xx 0 0 0011 43 xx xx 89 00 03 40 xx xx xx xx 44 xx 10 xx xx 0 1 0010 43 xx xx 10 xx021 48 xx xx xx xx 52 xx xx 20 46 0 1 1100 44 46 20 xx xx 1c 56 48 45 42 45 0 0 1111 45 45 42 45 48 0f 60 4c 45 46 46 0 0 1111 46 46 46 45 4c 0f 64 43 43 41 43 0 0 1111 47 43 41 43 41 0f 68 41 43 41 43 0 0 1111 48 43 41 43 41 0f 72 41 43 41 43 0 0 1111 49 43 41 43 41 0f 76 41 43 41 43 0 0 1111 50 43 41 43 41 0f 80 41 43 41 43 0 0 1111 51 43 41 43 41 0f 84 41 xx xx xx 1 0 0001 52 xx xx xx 41 81 table 41. pmr programming example 132 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3.10.17.1 h_reset hardware reset (h_reset) occurs when the reset_l signal is asserted. when the minimum pulse width timing as speci?d in the reset_l signal description has been satis?d, an internal reset operation is performed. h_reset programs most of the internal registers to their default values. note that there are several register ?lds that are unde?ed after h_reset. see the descriptions of the individual registers for details. h_reset clears most of the registers in the pci con?uration space. h_reset resets the internal state machines. to allow the lan ethernet controller to report wake-up events while operating in the d3cold state, the internal h_reset signal is blocked and no internal reset occurs when dev1:0x44[pwrstat] is 3h. this allows wake-up logic to function correctly when reset_l is asserted in s3-5. an internal h_reset signal is automatically generated and a reset operation occurs when dev1:0x44[pwrstat] is changed from 3h to any other value. 3.10.17.2 run reset a run reset is generated when the value of the run bit (cmd0, bit 0) is changed from 1 to 0. run reset resets most of the bits in cmd0 and int0. run reset terminates all network activity abruptly and resets the internal state machines. the host can use the suspend mode (tx_spnd and rx_spnd in cmd0) to terminate all network activity in an orderly sequence before clearing the run bit. 3.10.17.3 power up reset power up reset is generated when power is ?st applied to the network controller or when clock to the controller is enabled (see devb:3x64). the assertion of this signal generates a hardware reset (h_reset). in addition, it clears certain power management bits in pci_pmcsr, cmd7, and stat0 that h_reset does not affect. 3.10.17.4 external phy reset the phy_rst pin is intended to be connected to the reset input of an external phy that does not have its own power on reset capability. the polarity of phy_rst is determined by the phy_rst_pol bit in cmd3. the host cpu can cause the phy_rst pin to be asserted by setting the reset_phy or the reset_phy_pulse pin in cmd3. the phy_rst pin remains asserted as long the reset_phy bit has the value 1. if the reset_phy_pulse bit is set, the phy_rst pin remains asserted for a time determined by the contents of the reset_phy_width ?ld in ctrl1 (bits 23:16). reset_phy_pulse is a read-only bit that does not have to be cleared. the reset_phy and the reset_phy_pulse bits should not be set at the same time. chapter 3 functional operation 133 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 134 functional operation chapter 3 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information chapter 4 registers 135 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information chapter 4 registers 4.1 register overview the ic includes several sets of registers accessed through a variety of address spaces. i/o address space refers to register addresses that are accessed by x86 i/o instructions such as in and out. pci con?uration space is typically accessed by pci-de?ed i/o cycles to cf8h and cfch in the host. there is also memory space and indexed address space in the ic. 4.1.1 con guration space the address space for pci con?uration registers is broken up into buses , devices , functions , and, offsets , as de?ed by the pci speci?ation. the ic can be con?ured to include con?uration space on two buses, the primary and secondary. the con?uration space on the primary (host) bus is accessed by type 0 con?uration cycles (as de?ed by the pci and hypertransport technology speci?ations). in hypertransport technology mode, the device number is mapped into bits[15:11] of the con?uration address. the function number is mapped into bits[10:8] of the con?uration address. the offset is mapped to bits[7:2] of the con?uration address. type 1 con?uration cycles on the host bus that are targeted to internal or external devices on the secondary pci bus are converted to type 0 con?uration cycles. the ic is viewed by software as two pci bus devices that sit on the primary bus, typically bus 0. the ?st device number?hich matches the assigned base hypertransport link unitid number for the part?s the pci bridge and the second is the lpc bridge. since the usb and ethernet controllers reside on the secondary pci bus, their device numbers are hard wired to 0 through 1 on that bus. the remaining device numbers through 15 are available on the external bus, per the pci-to-pci bridge speci?ation. con?uration cycles to device numbers 16 through 31 on the secondary pci bus are generated with address bits[31:11] all zero so no idsel lines are set. the following diagram shows where all the functions reside in con?uration space. 136registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information figure 30. con guration space (primary and secondary bus) con?uration accesses to non-existent functions or functions disabled by devb:0x48[priens] within device a and b are not claimed by the ic. con?uration writes to non-existent registers within each enabled function are ignored and reads return all zeros. 4.1.2 register naming and description conventions each register location has an assigned mnemonic that speci?s the address space and offset. these mnemonics start with two or three characters that identify the space followed by characters that identify the offset within the space. register ?lds within register locations are also identi?d with a name or bit group in brackets following the register location mnemonic. for example, the acpi sleep type register ?ld, which is located at offset 04h of pmxx space, bits10, 11, and 12, is referenced as pm04[slp_typ] or pm04[12:10]. pci con?uration spaces are referenced with mnemonics that take the form of dev[a|b|0|1|2|3]:[7:0]x[ff:0], where the ?st bracket contains the device number identi?r, the second bracket contains the function number, and the last bracket contains the offset. device numbers on the primary and secondary bus are assigned by the platform designer by programming deva:0xc0[buid]. table 43. pci con guration spaces bus device function mnemonic functionality primary buid 0 deva:0xxx pci bridge primary buid+1 0 devb:0xxx lpc bridge, legacy circuitry primary buid+1 1 devb:1xxx enhanced ide controller primary bus pci bridge deva:0xxx bridge header function 0 first device usb 0 dev0:0xxx function 0 device 0 secondary bus external pci bus devices ehc usb 1 dev0:1xxx function 1 device 0 dev0:2xxx function 2 device 0 lpc bridge devb:0xxx device header function 0 second device ide controller devb:1xxx function 1 smbus2.0 controller devb:2xxx function 2 system management devb:3xxx function 3 ac 97 audio devb:5xxx function 5 ac 97 modem devb:6xxx function 6 ipb controller devb:7xxx function 7 dev1:0xxx function 0 device 1 controller lan ethernet chapter 4 registers 137 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information primary buid+1 2 devb:2xxx smbus 2.0 controller primary buid+1 3 devb:3xxx system management registers primary buid+1 5 devb:5xxx ac 97 soft audio controller primary buid+1 6 devb:6xxx ac 97 soft modem controller secondary 0 0 dev0:0xxx ohci-based usb controller 0 secondary 0 1 dev0:1xxx ohci-based usb controller 1 secondary 0 2 dev0:2xxx ehci-based usb controller secondary 1 0 dev1:0xxx lan ethernet controller table 44. fixed address spaces port(s) mnemonic type function 00-0f portxx i/o mapped slave dma controller 20-21 portxx i/o mapped master interrupt controller 40-43 portxx i/o mapped programmable interval timer 60 port60 i/o mapped usb keyboard emulation address 61 port61 i/o mapped at compatibility register 64 port64 i/o mapped usb keyboard emulation address 70-73 rtcxx i/o mapped real-time clock and cmos ram 80-8f portxx i/o mapped dma page registers 92 port92 i/o mapped system control register a0-a1 portxx i/o mapped slave interrupt controller c0-df portxx i/o mapped master dma controller f0-f1 portxx i/o mapped floating-point error control 170-177, 376 portxx i/o mapped secondary ide drives (not used when in native mode) 1f0-1f7, 3f6 portxx i/o mapped primary ide drives (not used when in native mode) 4d0-4d1 port4d0 i/o mapped eisa-de ned level-triggered interrupt control registers cf9 portcf9 i/o mapped reset register fec0_00xx ioaxx memory mapped ioapic register set table 43. pci con guration spaces 138 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information the following are register behaviors found in the register descriptions. 4.1.3 positively- and subtractively-decoded spaces the ic positively decodes all address ranges described above as well as address windows for the secondary pci bus, speci?d by the pci bridge header. all transactions received that are not positively decoded are passed either directly to the lpc bridge or provided onto the secondary pci table 45. relocatable address spaces address specified by configuration register size (bytes) type mnemonic function devb:0x74 256 i/o mapped none pointer to 256 bytes of non volatile ram devb:0xa0 1024 memory mapped hpetxx high precision event timer control registers devb:0xa8 32 memory mapped wdtxx watchdog timer control registers devb:1x10 1 8 i/o mapped none pointer to primary port ide command space devb:1x14 1 4 i/o mapped none pointer to primary port ide control space devb:1x18 1 8 i/o mapped none pointer to secondary port ide command space devb:1x1c 1 4 i/o mapped none pointer to secondary port ide control space devb:1x20 16 i/o mapped ibmx ide controller bus-master control registers devb:2x10 32 i/o mapped scxx smbus controller command register space devb:3x58 256 i/o mapped pmxx system management i/o register space devb:5x10 256 i/o mapped none pointer to ac 97 audio mixer space devb:5x14 64 i/o mapped acxx ac 97 audio bus master control registers devb:6x10 256 i/o mapped none pointer to ac 97 modem mixer space devb:6x14 64 i/o mapped mcxx ac 97 modem bus master control registers dev0:0x10 4k memory mapped none usb ohc control registers dev0:1x10 4k memory mapped none usb ohc control registers dev0:2x10 256 memory mapped ecap usb ehc capability registers dev0:2x14 256 memory mapped dbg usb ehc debug port registers dev1:0x10 4k memory mapped enc ethernet controller memory space notes: 1. devb:1x10, devb:1x14, devb:1x18, and devb:1x1c are only used when the ide controller is in native mode as speci?d by devb:1x08. table 46. register behavior types (read, write, etc.) type description read or read-only capable of being read by software. read-only implies that the register cannot be written to by software. write capable of being written by software. set by hardware register bit is set high by hardware. write 1 to clear software must write a 1b to the bit in order to clear it. writing a 0b to these bits has no effect. write 1 only software can set the bit high by writing a 1b to it. however subsequent writes of 0b have no effect. reset_l must be asserted in order to clear the bit. write once after reset_l, these registers may be written to once. after they are written, they become read-only until the next reset_l assertion. chapter 4 registers 139 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information bus before being sent to the lpc bus (see devb:0x40[subdec]). thus, the lpc bridge is the subtractive decode path for all unclaimed cycles. 4.2 pci bridge con guration registers (deva:0xxx) these registers are located in pci con?uration space on the primary pci interface, in the ?st device (device a), function 0. see section 4.1.2 on page 136 for a description of the register naming convention. pci bridge vendor and device id register deva:0x00 default: 7460 1022h attribute: read-only pci bridge status and command register deva:0x04 default: 0230 0000h. attribute: see below. bits description 31:16 pci bridge device id 15:0 vendor id bits description 31 dpe. detected parity error. this bit is xed in the low state. 30 sse. signaled system error. read; set by hardware; write 1 to clear (however, software cannot get to this register until after reset). 1=a system error was signaled to the host (the outgoing hypertransport link was ooded with sync packets) as a result of: a crc error (see deva:0xc4[crcfen, crcerr]) or a discard timer error (see deva:0x3c[dtserren, dtstat]) or an address parity error of a transaction targetted to the pci bridge (see deva:0x3c[serren]) or serr_l assertion (see deva:0x3c[serren]). note: this bit is cleared by pwrok reset but not by reset_l. 29 rma. received master abort. read; set by hardware; write 1 to clear. 1=a request sent to the host bus received a master abort (an nxa error response). note: this bit is cleared by pwrok reset but not by reset_l. 28 rta. received target abort. read; set by hardware; write 1 to clear. 1=a request sent to the host bus received a target abort (a non-nxa error response). note: this bit is cleared by pwrok reset but not by reset_l. 27 signaled target abort. read-only. this bit is xed in the low state. 26:25 devsel timing. read-only. these bits are xed at status[10:9] = 01b. this speci es medium timing as de ned by the pci speci cation. 24 data parity detected. read-only. this bit is xed in the low state. 23 fast back-to-back enable. read-only. this bit is xed in the low state. 22 user de nable features. read-only. this bit is xed in the low state. 140 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information pci bridge revision and class code register deva:0x08 default: 0604 00xxh see below. attribute: read-only. pci bridge bist-header-latency-cache register deva:0x0c default: 0001 0000h. attribute: see below. pci bridge bus numbers and secondary latency register deva:0x18 default: 0000 0000h. attribute: read-write. 21 66 mhz capable. read-only. this bit is xed in the high state. 20 capabilities pointer. read-only. this bit is xed in the high state. 19:9 reserved 8 serren. serr_l enable. read-write. see deva:0x3c[serren]. 7 reserved. 6 persp. parity error response. read-write. this bit controls no hardware. 5 reserved. 4 mwien. memory write and invalidate enable. read-write. this bit does not control any internal hardware. 3 special cycle enable. read-only. this bit is hardwired low. 2 masen. pci master enable. read-write. 1=enables internal and external pci secondary bus masters to initiate cycles to the host. 1 memen. memory enable. read-write. 1=enables access to the secondary pci bus memory space. 0 ioen. i/o enable. read-write. 1=enables access to the secondary pci bus i/o space. bits description 31:8 classcode. provides the bridge class code as de ned in the pci speci cation. this eld is write accessible through deva:0x60. 7:0 revision. pci bridge silicon revision. the value of this register is revision-dependent. bits description 31:24 bist. read-only. these bits xed at their default values. 23:16 header. read-only. these bits xed at their default values. 15:8 latency. read-write. these bits control no hardware. 7:0 cache. read-only. these bits xed at their default values. bits description 31:24 seclat. secondary latency timer. 23:16 subbus. subordinate bus number. 15:8 secbus. secondary bus number. 7:0 pribus. primary bus number. bits description (continued) chapter 4 registers 141 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information pci bridge memory base-limit registers deva:0x1c, deva:0x20 and deva:0x24 these registers specify the i/o-space (deva:0x1c), non-prefetchable memory-space (deva:0x20), and prefetchable memory-space (deva:0x24) address windows for transactions that are mapped to the secondary pci bus as follows: pci i/o window = {16'h0000,deva:0x1c_iolim,12'hfff} >= address >= {16'h0000,deva:0x1c_iobase,12'h000}; pci non-prefetchable memory window = {deva:0x20_memlim,20'hf_ffff} >= address >= {deva:0x20_membase,20'h0_0000}; pci prefetchable memory window = {deva:0x24_pmemlim,20'hf_ffff} >= address >= {deva:0x24_pmembase,20'h0_0000}; these windows may also be altered by deva:0x3c[vgaen, isaen]. when the address (from either the host or from a secondary pci bus master) is inside one of the windows, then the transaction is assumed to be intended for a target that sits on the secondary pci bus. therefore, the following transactions are possible: host-initiated transactions inside the windows are sent to the pci bus. secondary pci-initiated transactions inside the windows are not claimed by the ic. host initiated transactions outside the windows that are not claimed by any other functions within the ic are passed to the lpc bus. secondary pci initiated transactions outside the windows are claimed by the ic using medium decoding and passed to the host. if iobase > iolim, membase > memlim, and pmembase > pmemlim, then no host- initiated transactions are forwarded by the secondary pci bus and all secondary-pci-bus-initiated memory and i/o (not con?uration) transactions are forwarded to the host. deva:0x1c default: 0200 00f0h. attribute: see below. bits description 31 dpe. detected parity error. read; set by hardware; write 1 to clear. 1=the ic detected an address parity error as the target of a secondary pci bus cycle or a data parity error as the target of a secondary pci bus write cycle or a data parity error as the master of a secondary pci bus read cycle. 30 rse. received system error. read; set by hardware; write 1 to clear. 1=the ic detected assertion of serr_l. note: this bit is cleared by pwrok reset but not by reset_l. 29 rma. received master abort. read; set by hardware; write 1 to clear. 1=the ic received a master abort as a master on the secondary pci bus. note: this bit is cleared by pwrok reset but not by reset_l. 28 rta. received target abort. read; set by hardware; write 1 to clear. 1=the ic received a target abort as a master on the secondary pci bus. note: this bit is cleared by pwrok reset but not by reset_l. 142 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information deva:0x20 default: 0000 fff0h. attribute: read-write. deva:0x24 default: 0000 fff0h. attribute: read-write. pci bridge subsystem id and subsystem vendor id register deva:0x2c default: 0000 0000h. attribute: read-only. 27 sta. signaled target abort. read; set by hardware; write 1 to clear. 1=the ic generated a target abort as a target on the secondary pci bus. the ic generates a target abort if it receives a target abort (a non-nxa error) response from the host to a secondary pci master transaction request. note: this bit is cleared by pwrok reset but not by reset_l. 26:25 device select timing. read-only. these bits are hard wired to indicate medium decoding. 24 mdpe. master data parity error. read; set by hardware; write 1 to clear. 1=the ic detected a parity error during a data phase of a read or detected perr_l asserted during a write as a master on the secondary pci bus and deva:0x3c[peren] is set. when this bit is set, an nmi is generated; see pm48[nmi2smi_en] for information on how nmi interrupts may be controlled. 23:16 reserved. 15:12 iolim. i/o limit address bits. [15:12]. see deva:0x[24:1c] above. 11:8 reserved. 7:4 iobase. i/o base address bits. [15:12]. see deva:0x[24:1c] above. 3:0 reserved. bits description 31:20 memlim. non-prefetchable memory limit address bits. [31:20]. see deva:0x[24:1c] above. 19:16 reserved. 15:4 membase. non-prefetchable memory base address bits. [31:20]. see deva:0x[24:1c] above. 3:0 reserved. bits description 31:20 pmemlim. prefetchable memory limit address bits. [31:20]. see deva:0x[24:1c] above. 19:16 reserved. 15:4 pmembase. prefetchable memory base address bits. [31:20]. see deva:0x[24:1c] above. 3:0 reserved. bits description 31:16 ssid. subsystem id. this eld is write accessible through deva:0x70. 15:0 ssvendorid. subsystem vendor id. this eld is write accessible through deva:0x70. chapter 4 registers 143 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information hypertransport technology capabilities pointer register deva:0x34 default: 0000 00c0h. attribute: read-only. pci bridge interrupt and bridge control register deva:0x3c default: 0000 00ffh. attribute: see below. bits description 31:8 reserved. 7:0 capabilities_ptr. speci es the offset to standard hypertransport technology registers. bits description 31:28 reserved. 27 dtserren. discard timer serr_l enable. read-write. this bit speci es if a system error is issued on discard timer expiration. 1= enable system error. 0= no error is agged on discard timer expiration. note: a system error is only agged if deva:0x04[serren] is set. this ic signals a system error by a sync ood on the hypertransport link which also sets deva:0x04[sse]. 26 dtstat. discard timer status. read; set by hardware; write 1 to clear. 1= the ic detected the expiration of the secondary discard timer. note: this bit is cleared by pwrok reset but not by reset_l. 25 secdtv. secondary discard timer value. read-write. this bit speci es after how many clocks a received response for a delayed request gets discarded. 1= the discard timer counts 2 10 pci clock cycles. 0= the discard timer counts 2 15 pci clock cycles. 24:23 reserved. 22 read-write. this bit controls no hardware. 21 marsp. master abort response. read-write. 1=the response to non-posted requests that come from the host bus or secondary pci bus that results in a master abort indicates a target abort (through pci bus protocol or hypertransport link protocol). 0=master aborts result in normal responses; read responses are sent with the appropriate amount of data, which are all 1 s and writes are ignored. 20 reserved. 19 vgaen. vga decoding enable. read-write. 1=route host-initiated commands targeting vga- compatible address ranges to the secondary pci bus. these include memory accesses from a0000h to bffffh, i/o accesses in which address bits[9:0] range from 3b0h to 3bbh or 3c0h to 3dfh (address bits[15:10] are not decoded, regardless of bit[18], isa enable). 0=pci does not decode vga-compatible address ranges. 18 isaen. isa decoding enable. read-write. 1=the i/o address window speci ed by deva:0x1c[15:0] is limited to the rst 256 bytes of each 1k byte block speci ed. 0=the pci i/o window is the whole range speci ed by deva:0x1c[15:0]. 144 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information system management class code write register deva:0x60 default: 0604 0000h. attribute: read-write. device and subsystem id read-write register deva:0x70 default: 0000 0000h. attribute: read-write. hypertransport technology command register deva:0xc0 default: 0080 f008h. attribute: see below. 17 serren. system error enable. read-write. if deva:0x04[serren] and deva:0x3c[serren] are both high and if: an address parity error of a transactions targetted to the pci bridge is detected, or serr_l is detected asserted (deva:0x1c[rse] = 1), then the ic responds by ooding the outgoing link with sync packets and setting deva:0x04[sse]. if either deva:0x04[serren] or deva:0x3c[serren] are low, then neither of the two events above stops hypertransport link operation or causes deva:0x04[sse] to be set. 16 peren. parity error response enable. read-write. 1=enable parity error detection on secondary pci interface (see deva:0x1c[mdpe]); perr_l signal enabled to set status bit or be driven. 0=deva:0x1c[mdpe] cannot be set; perr_l signal is ignored and it is not driven by the ic. 15:8 interrupt_pin. read-only. these bits xed in their default state. 7:0 interrupt_line. read-write. these bits control no internal logic. bits description 31:8 ccwrite. the value placed in this register is visible in deva:0x08. 7:0 reserved. bits description 31:16 ssid. subsystem id. the value placed in this register is visible deva:0x2c[31:16]. 15:0 ssvendorid. subsystem vendor id. the value placed in this register is visible deva:0x2c[15:0]. bits description 31:29 slave/primary interface type. read-only. 28 drop on unitialized link. read-write. this bit controls no internal hardware. note: this bit is cleared by pwrok reset but not by reset_l. 27 default direction. read-only. this bit is hardwired low to indicate that requests are sent to the master hypertransport host bridge. 26 master host. read-only. this bit is hardwired low to indicate that the master is connected to link 0. bits description (continued) chapter 4 registers 145 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information hypertransport link control register deva:0xc4 default: ??00 0020h; see below for the default of bits[31:24]. attribute: see below. 25:21 unit id count. read-only. speci es the number of unit ids used by the ic. 20:16 buid. base unitid. read-write. this speci es the hypertransport protocol base unit id. the ic's logic uses this value to determine the unit ids for hypertransport request and response packets. 15:8 capabilities pointer. read-only. this register contains the pointer to the hypertransport interrupt discovery and con guration capability. 7:0 capabilities id. read-only. speci es the capabilities id for hypertransport technology con guration space. bits description 31 reserved. 30:28 lwo. link width out. read-write. speci es the operating width of the outgoing hypertransport link. legal values are 000b (8 bits), 100b (2 bits), and 101b (4 bits). writes of invalid values do not change the register content and are ignored. note: this eld is cleared by pwrok reset but not by reset_l; the default value of this eld depends on the widths of the hypertransport links of the connecting device, as speci ed by the hypertransport speci cation. note: the link width does not change until either reset_l is asserted or a hypertransport link disconnect sequence occurs. 27 reserved. 26:24 lwi. link width in. read-write. speci es the operating width of the incoming hypertransport link. legal values are 000b (8 bits), 100b (2 bits), and 101b (4 bits). writes of invalid values do not change the register content and are ignored. note: this eld is cleared by pwrok reset but not by reset_l; the default value of this eld depends on the widths of the hypertransport links of the connecting device, as speci ed by the hypertransport speci cation. note: the link width does not change until either reset_l is asserted or a hypertransport link disconnect sequence occurs. 23 reserved. 22:20 max link width out. read-only. this speci es the width of the outgoing hypertransport link to be 8 bits wide. 19 reserved. 18:16 max link width in. read-only. this speci es the width of the incoming hypertransport link to be 8 bits wide. 15 reserved. 14 extctl. extended control time. read-write. this bit speci es the time in which ltxctl_h/l is held asserted during the initialization sequence that follows a ldtstop_l deassertion, after lrxctl_h/l is sampled asserted. 1= about 50 microseconds. 0= at least 16 bit times (for a 8 bit link). note: this bit is cleared by pwrok reset but not by reset_l. 13 ldt3sen. hypertransport link three-state enable. read-write. 1=during the ldtstop_l disconnect sequence, the hypertransport transmitter signals are placed into the high impedance state and the receivers are prepared for the high impedance mode. 0=during the ldtstop_l disconnect sequence, the hypertransport transmitter signals are driven, but in an unde ned state, the hypertransport clock is toggling, and the hypertransport receiver signals are assumed to be driven. note: this bit is cleared by pwrok reset but not by reset_l. 12:9 reserved. 8 crcerr. crc error. read; set by hardware; write 1 to clear. 1=the hardware detected a crc error on the incoming hypertransport link. note: this bit is cleared by pwrok reset but not by reset_l. 7 txoff. transmitter off. read-only (not implemented). 146registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information hypertransport non-existent link control register deva:0xc8 default: 0000 00d0h. attribute: read-only. 6 endoch. end of chain. read-only (not implemented). 5 initcplt. initialization complete. read-only; set by hardware; cleared by reset_l. this bit is set by hardware when low-level link initialization has successfully completed. if there is no device on the other end of the link, or if that device is unable to properly perform link initialization, the bit is not set. 4 lkfail. hypertransport link failure. read; set by hardware; write 1 to clear. this bit is set high by the hardware when a crc error is detected on the link (if enabled by deva:0xc4[crcfen]). note: this bit is cleared by pwrok reset but not by reset_l. 3 crcerrcmd. crc error command. read-write. 1=the hypertransport transmission logic generates erroneous crc values. 0=transmitted crc values match the values calculated per the hypertransport speci cation. this bit is intended to be used to check the crc failure detection logic of the device on the other side of the link. 2 reserved. 1 crcfen. crc ood enable. read-write. 1=crc errors result in sync packets to the outgoing hypertransport link and set the deva:0xc4[lkfail] bit. 0=crc errors do not result in sync packets and do not set the link fail bit. 0 reserved. bits description 31:8 reserved. 7 transmitter off. this bit is hardwired high to indicate that there is no subordinate hypertransport link. 6 end of hypertransport chain. this bit is hardwired high to indicate that there is no subordinate hypertransport link. 5 reserved. 4 link failure. this bit is hardwired high to indicate that there is no subordinate hypertransport link. 3:0 reserved. bits description (continued) chapter 4 registers 147 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information hypertransport technology revision id register deva:0xcc default: 0001 0022h. attribute: see below. hypertransport technology feature register deva:0xd0 default: 0000 0002h (see below). attribute: read-only. hypertransport technology enumeration scratchpad register deva:0xd4 default: 0000 0000h. attribute: see below. bits description 31:16 link frequency capability. read-only. these bits indicate that the ic supports 200 mhz hypertransport clock. 15:12 link error. read-only. these bits are hard wired to the low state. 11:8 linkfreq. link frequency. these bits control the frequency of the hypertransport link. legal value is 0000b (= 200 mhz). writes of invalid values does not change the register content and are ignored. note: this bit is cleared by pwrok reset, not by reset_l. note: after this eld is updated, the link frequency does not change until either reset_l is asserted or a disconnect sequence occurs. 7:0 revision. read-only. the ic is designed to version 1.02 of the hypertransport technology speci cation. exceptions to the 1.02 hypertransport technology speci cation are: - no crc test support. - no support for memory accesses over 32 bits. bits description 31:2 reserved. 1 lssup. ldtstop_l supported. this bit is high to indicate that the ic supports the ldtstop_l signal. 0 reserved. bits description 31:16 reserved. 15:0 esp. enumeration scratchpad. read-write. this eld controls no hardware within the ic. note: these bits are cleared by pwrok reset, not by reset_l. 148 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information hypertransport link phy compensation control registers deva:0x[e8, e4, e0] the hypertransport phy circuitry includes automatic compensation that is used to adjust the electrical characteristics for the hypertransport transmitters and receivers. there is one compensation circuit for the receivers and one for each polarity of the transmitters. these registers provide visibility into the calculated output of the compensation circuits, the ability to override the calculated value with software-controlled values, and the ability to offset the calculated values with a ?ed difference. these registers specify the compensation parameters as follows: deva:0xe0: transmitter rising edge (p) drive strength compensation. deva:0xe4: transmitter falling edge (n) drive strength compensation. deva:0xe8: receiver impedance compensation. for deva:0x[e4, e0], higher values represent higher drive strength; the values range from 00h to 13h (20 steps). for deva:0xe8, higher values represent lower impedance; the values range from 00h to 1fh (32 steps). note: the default state of these registers is set by pwrok reset; assertion of reset_l does not alter any of the ?lds. default: see below. attribute: see below. bits description 31 must be low. read-write. this bit is required to be low at all times; setting it high results in unde ned behavior. 30:21 reserved. 20:16 calccomp. calculated compensation value. read-only. this provides the calculated value from the auto compensation circuitry. the default value of this eld is not predictable. 15:7 reserved. 6:5 ctl. hypertransport phy control value. read-write. these two bits combine to specify the phy compensation value as follows: ctl description 00b apply calccomp directly as the compensation value. 01b apply data directly as the compensation value. 10b apply the sum of calccomp and data as the compensation value. in deva:0x[e4, e0], if the sum exceeds 13h, then 13h is applied. in deva:0x[e8], if the sum exceeds 1fh, then 1fh is applied. 11b apply the difference of calccomp minus data as the compensation value. if the difference is less than 00h, then 00h is applied. the default value of this eld (from pwrok reset) is controlled by devb:3x48[cmpovr]. if cmpovr = 0, the default is 00b. if cmpovr = 1, the default is 01b. 4:0 data. hypertransport phy data value. read-write. this value is applied to the hypertransport phy compensation as described in ctl. the default for deva:0x[e4, e0] is 08h. the default for deva:0xe8 is 0fh. chapter 4 registers 149 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information read-write register deva:0xec default: 0000h. attribute: read-write. hypertransport technology interrupt discovery and con guration capability register deva:0xf0 default: 8000 0008h attribute: see below. hypertransport technology interrupt register dataport deva:0xf4 default: 0000_0000h. attribute: read-write. 4.3 lpc bridge con guration registers (devb:0xxx) these registers are located in pci con?uration space on the primary pci interface, in the second device (device b), function 0. see section 4.1.2 on page 136 for a description of the register naming convention. lpc bridge vendor and device id register devb:0x00 default: 7468 1022h. attribute: read-only. bits description 15:0 rw. read-write . these bits are read-write accessible through software; they control no hardware. bits description 31:29 captype. capability type. read-only. this register is hardwired to 100b to indicate this is the interrupt discovery and con guration capability. 28:24 reserved. 23:16 iridx. interrupt register index. read-write. this register select the register which is accessed through the interrupt register dataport. 15:8 capptr. capability pointer. read-only. this register is hardwired to 0. 7:0 capid. capabilities id. read-only. speci es the capabilities id for hypertransport technology con guration space. bits description 31:0 irdp. interrupt register dataport. read-write. this register provides access to the interrupt register which is speci ed by the index register iridx. only doubleword access to this register is supported. bits description 31:16 lpc bridge device id 15:0 vendor id 150 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lpc bridge status and command register devb:0x04 default: 0220 000fh. attribute: see below. lpc bridge revision and class code register devb:0x08 default: 0601 00xxh see below. attribute: read-only. lpc bridge bist-header-latency-cache register devb:0x0c default: 0080 0000h. attribute: read-only. lpc bridge subsystem id and subsystem vendor id register devb:0x2c default: 0000 0000h. attribute: read-only. bits description 31:4 hardwired to default values. 3 spcycen. special cycle enable. read-write. 1=the ic responds to shutdown special cycles by using init to reset the processor. 0=the ic ignores shutdown special cycles. 2:0 i/o, memory, and master enable. read-only. hardwired in the enabled state. bits description 31:8 classcode. provides the isa bridge class code as de ned in the pci speci cation. 7:0 revision. lpc bridge silicon revision . the value of this register is revision-dependent. bits description 31:24 bist. these bits xed at their default values. 23:16 header. these bits xed at their default values. 15:8 latency. these bits xed at their default values. 7:0 cache. these bits xed at their default values. bits description 31:16 ssid. subsystem id. this eld is write accessible through devb:0x70. 15:0 ssvendorid. subsystem vendor id. this eld is write accessible through devb:0x70. chapter 4 registers 151 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information i/o control 1 register devb:0x40 default: 00h. attribute: see below. i/o control 2 register devb:0x41 default: 00010?00b. (pin-strap: see below) attribute: see below. bits description 7 nmionerr. generate an nmi on error. read-write. 1=an nmi is generated when one of the error status bits speci ed by section 3.1.2 on page 37 is set. note: see pm48[nmi2smi_en] for information on how nmi interrupts may be controlled. 6 lpcerr. lpc transaction error status. read; set by hardware; write 1 to clear. the bit is set high by hardware when an lpc sync error occurs. 5 subdec. subtractive decoding off of the secondary pci bus. read-write. 1=all memory mapped and i/o mapped transactions received by the host that are not destined for any internally speci ed devices or buses are sent to the secondary pci bus; if devsel_l is not asserted for these pci bus cycles, then the ic asserts devsel_l during the subtractive window, and asserts stop_l to complete the cycle; the cycle is then retransmitted to the lpc bus; if, during the pci bus cycle, devsel_l is asserted by an external component before the subtractive window, then the cycle is assumed to be for the secondary pci bus and allowed to complete. 0=all memory mapped and i/o mapped transactions received by the host that are not destined for any internally speci ed devices or buses are sent directly to the lpc bus. 4 lpc_ior. lpc i/o recovery. read-write. 1= i/o recovery delay (speci ed by iort) enforced for both lpc and legacy i/o cycles. 0=i/o recovery delay only enforced for legacy i/o cycles (cycles to the dma controller, legacy pic, programmable interval timer, and real-time clock). 3 iort. i/o recovery time. read-write. this bit speci es the amount of time enforced between internal legacy i/o cycles (cycles to the dma controller, legacy pic, programmable interval timer, and real- time clock) and, if enabled by lpc_ior, lpc cycles. 0=there are a minimum of 22 pclk cycles between the end of each i/o cycle and the beginning of the next i/o cycle. 1=there are a minimum of 54 pclk cycles between i/o cycles. this bit does not affect memory cycles (only i/o cycles). 2 ble. bios lock enable. read; write 1 only. 1=setting devb:0x40[rwr] from 0 to 1 sets pm44[ibios_sts] and generates an smi. 0=setting devb:0x40[rwr] from 0 to 1 does not set pm44[ibios_sts] and does not generate an smi. once ble is set, it can only be cleared by reset_l. 1 pw2lpc. discarded posted request targeting lpc. read; set by hardware; write 1 to clear. this bit is set by hardware if a posted request that targets a device on the lpc gets discarded. this can only be set if devb:0x41[dpw2lpc] is programmed high. setting this bit can result in a nmi if enabled with devb:0x40[nmionerr]. 0 rwr. lpc rom write. read-write. 1=memory writes to bios rom address space, as de ned by devb:0x43, are allowed to pass onto the lpc bus. 0=memory writes to bios rom address space are dropped. bits description 7 reserved. 6 reserved. 5 p92fr. port 92 fast reset. read-write. 1=writes that attempt to set i/o port92[0] the fast processor reset bit are enabled. 0=writes to port92[0] do not generate a processor reset pulse using the hypertransport technology init interrupt. 152 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 4 dpw2lpc. discard posted writes targeting lpc. read-write. 1=posted writes targeting the lpc while a lpc bus master or dma cycle is in progress get discarded. 0=posted writes are passed to the lpc. 3 specen. special cycle enable onto secondary pci bus. read-write. 1=special cycles received from the host are passed to the secondary pci bus. 0=no special cycles are passed to the secondary pci bus. the supported special cycles and the associated eld of the pci data phase are: shutdown: 0000_0000h. halt: 0000_0001h. writeback invalidate 0001_0002h. invalidate 0002_0002h. enter smm: 0005_0002h. exit smm: 0006_0002h. vid/fid change 0007_0002h. stop grant: 0012_0002h. thermal trip point crossed 0014_0002h. ferr_l asserted 0021_0002h. ferr_l deasserted 0022_0002h. 2 must be low . read-write. this bit is required to be low at all times; setting it high results in unde ned behavior. 1 nmidis. nmi disable. read-only. this provides read access to rtc70[nmidis]. 0 shen. shadow register access enable. read-write. 1=shadowed i/o access to legacy write-only registers is enabled. 0=normal access of legacy registers. the following table shows all registers affected by this bit. chapter 4 registers 153 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information table 47. registers affected by devb:0x41[shen] i/o port r/w normal mode shadow mode dma: 00h, 02h, 04h, w base address for dma channel current address for dma channel 06h, c0h, c4h, c8h, cch r current address for dma channel base address for dma channel dma: 01h, 03h, 05h, w base byte count for dma channel current byte count for dma channel 07h, c2h, c6h, cah, ceh r current byte count for dma channel base byte count for dma channel dma: 08h/d0h w command register dma ch[3:0]/ [7:4] status register dma ch[3:0]/[7:4] r status register dma ch[3:0]/[7:4] first read: command reg dma ch[3:0]/ [7:4] second read: request reg dma ch[3:0]/ [7:4] third read: mode register dma ch0/4 fourth read: mode register dma ch1/5 fifth read: mode register dma ch2/6 sixth read: mode register dma ch3/7 dma: 09h/d2h, 0ah/ d4h, 0bh/d6h w see dma controller reserved dma: 0ch/d8h, 0dh/ dah, 0eh/dch w see dma controller same as normal mode dma: 0fh/deh w write all masks [3:0]/[7:4] write all masks [3:0]/[7:4] r reserved read all masks [3:0]/[7:4] pit: 40h r status byte counter 0 first read: status byte counter 0 second read: crl for counter 0 third read: crm for counter 0 fourth read: crl for counter 1 fifth read: crm for counter 1 sixth read: crl for counter 2 seventh read: crm for counter 2 pit: 41h r status byte counter 1 status byte counter 1 pit: 42h r status byte counter 2 status byte counter 2 154 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information legacy blocks control register devb:0x42 default: 07h. attribute: read-write. pic: 20h r interrupt request register for pic 1 first read: icw1 for controller 1 second read: icw2 for controller 1 third read: icw3 for controller 1 fourth read: icw4 for controller 1 fifth read: ocw1 for controller 1 sixth read: ocw2 for controller 1 seventh read: ocw3 for controller 1 eighth read: icw1 for controller 2 ninth read: icw2 for controller 2 tenth read: icw3 for controller 2 eleventh read: icw4 for controller 2 twelfth read: ocw1 for controller 2 thirteenth read: ocw2 for controller 2 fourteenth read: ocw3 for controller 2 pic: 21h r in service register for pic 1 in service register for pic 1 pic: a0h r interrupt request register for pic 2 interrupt request register for pic 2 pic: a1h r in service register for pic 2 in service register for pic 2 bits description 7:3 reserved. 2 dmaen. internal dmac (direct memory access controller) enable. 1=enable internal 8237- based dmac and associated logic; accesses to i/o ports 00h through 0fh, 80h though 8fh, and c0h through dfh are routed to the internal dmac. 0=disable dmac and associated logic; dmac accesses are routed to the lpc bus. 1 piten. internal pit (programmable interval timer) enable. 1=enable internal 8254-based pit and associated logic; accesses to i/o ports 40h through 43h and 61h are routed to the internal pit. 0=disable pit and associated logic; pit accesses are routed to the lpc bus. 0 picen. internal pic (programmable interrupt controller) enable. 1=enable internal 8259-based pic and associated logic; accesses to i/o ports 20h, 21h, 92h, a0h, a1h, f0h, f1h, 4d0h, 4d1h as well as interrupt acknowledge cycles are routed to the internal pic and associated logic. 0=disable pic and associated logic; pic accesses are routed to the lpc bus. table 47. registers affected by devb:0x41[shen] (continued) chapter 4 registers 155 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information rom decode control register devb:0x43 default: 00h. attribute: read-write. segen. rom segment enables. this register speci?s the address space mapped to the bios rom on the lpc or pci bus (see devb:3x48[pcibios]). each bit speci?s if the lpc or pci bus is enabled for bios. for each of these bits: 1=enables an address range as a bios rom access. 0=the corresponding address range is not decoded as a bios rom access and not forwarded to the lpc or pci bus. writes to disabled segments are ignored and reads return all 0xf. the bits control the following address ranges (the last column shows the translated lpc bus addresses): note: the following ranges are always speci?d as bios address ranges. see devb:0x80 for more information about how access to bios spaces may be controlled. prefetchable memory control register devb:0x44 default: 0001h. attribute: read-write. bits size host address range[31:0] address translation for lpc bus 7 4 megabytes ffc0_0000h ffff_ffffh ffc0_0000h ffff_ffffh 6 1 megabyte ffb0_0000h ffbf_ffffh ffb0_0000h ffbf_ffffh 5 32k bytes 000e_8000h 000e_ffffh fffe_8000h fffe_ffffh 4 32k bytes 000e_0000h 000e_7fffh fffe_0000h fffe_7fffh 3 32k bytes 000d_8000h 000d_ffffh fffd_8000h fffd_ffffh 2 32k bytes 000d_0000h 000d_7fffh fffd_0000h fffd_7fffh 1 32k bytes 000c_8000h 000c_ffffh fffc_8000h fffc_ffffh 0 32k bytes 000c_0000h 000c_7fffh fffc_0000h fffc_7fffh size host address range[31:0] address translation for lpc bus 64k bytes ffff_0000h ffff_ffffh ffff_0000h ffff_ffffh 64k bytes 000f_0000h 000f_ffffh ffff_0000h ffff_ffffh bits description 15:4 tom[31:20]. top of memory bits[31:20]. this speci es the top of system memory. system memory space is treated as prefetchable by the pci bridge. it is de ned as follows: system_memory = (pci_address[31:20] <= tom[31:20]); note: if allpf is set high, then tom is ignored. 3:1 reserved. 0 allpf. all of memory space (4 gigabytes) is prefetchable. 1=all 4 gigabytes of memory space is prefetched by the pci bridge; when memory read transactions with pci command encoding of 6h are initiated by pci bus masters, then the data is prefetched, regardless of the address. 0=only memory read accesses with pci command encoding of ch or eh, or memory accesses with pci command encoding 6h below the top of memory speci ed in the tom eld of this register are prefetched. 156registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information miscellaneous control register devb:0x47 default: 00h. attribute: see below. bits description 7 ehcdis. enhanced host controller con guration space disable bit. read-write. 1= the ehc con guration space (dev0:2xxx) is disabled. reads return all 0xf (and an nxa error response) and writes are ignored (and return an nxa error response). 0= the ehc con guration space is enabled. note: if the ehc is disabled the ic is not capable to handle usb 2.0 traf c. 6 must be low. read-write. this bit is required to be low at all times; if it is high then unde ned behavior results. 5 alltod. all internal pci interrupts mapped to pirqd_l. read-write. 1=internal pci interrupts including the two usb interrupts, the ac 97 interrupts, the ethernet controller interrupt, the smbus 2.0 controller interrupt, the primary and secondary port (when these ports are in native mode) ide controller interrupts, and the gpio interrupts as speci ed by devb:0x4b[mpirq] are mapped to assert pirqd_l when they become active; i.e., all these interrupts are shared on pirqd_l. 0=internal pci interrupts are distributed across all four pirq[a,b,c,d]_l pins as speci ed in section 3.4.2.1 on page 41 and by devb:0x4b[mpirq]. 4 must be low. read-write. this bit is required to be low at all times; if it is high then unde ned behavior results. 3 cmlk_b8. cmos ram offsets b8b through bfh lock. read; write 1 only. 0=accesses to the eight bytes of cmos ram (powered by the vdd_coreal plane) addressed from b8h to bfh are read- write accessible. 1=writes to these bytes are ignored and read always return ffh (regardless as to which of the i/o ports from 70h to 73h are used for the access). after this bit is set high, it cannot be cleared again by software; it can only be cleared by pwrok reset. 2 cmlk_38. cmos ram offsets 38h through 3fh lock. read; write 1 only. 0=accesses to the eight bytes of cmos ram (powered by the vdd_coreal plane) addressed from 38h to 3fh are read- write accessible. 1=writes to these bytes are ignored and read always return ffh (regardless as to which of the i/o ports from 70h to 73h are used for the access). after this bit is set high, it cannot be cleared again by software; it can only be cleared by pwrok reset. 1 rstonle. reset on hypertransport link error. read-write. 1=assert the reset_l and ldtrst_l pins when either (1) a crc error is detected on the incoming hypertransport link (deva:0xc4[crcerr]) or (2) the incoming hypertransport link is ooded with sync packets. 0=hypertransport link errors do not result in resets. 0 swrst. software reset. write-only. when this bit is written with 1, a reset pulse is generated over reset_l and ldtrst_l. this bit always reads as 0. chapter 4 registers 157 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information function/device enable register devb:0x48 default: ffffh. attribute: read-write. ioapic con guration register 0 devb:0x4a default: 00h. attribute: read-write. ioapic con guration register 1 devb:0x4b default: 00h. attribute: read-write. bits description 15:8 secens[7:0]. secondary pci bus device enables. each of these bits apply to the rst 8 internal devices on the secondary pci bus. bit[0] applies to device 0, etc. bits that apply to device numbers that are not implemented internally are ignored. 1=the device's con guration space is enabled. 0=the device's con guration space is invisible; accesses to the space are master aborted; reads return all ones. 7:0 priens[7:0]. primary pci bus function enables. each of these bits apply to device b functions inside the ic (on the primary bus). bit[1] applies to function 1, bit[3] to function 3, etc. however, bit[0] is ignored since function 0 cannot be disabled. bits that apply to internal functions that do not exist in the ic are required to be low at all times; setting may result in unde ned behaviour. 1=the function's con guration space is enabled. 0=the function's con guration space is disabled; accesses to the space are master aborted and reads return all ones. bits description 7:2 reserved. 1 linten_nmi. local interrupt enable nmi. 1 = mt[3] is set in hypertransport link nmi interrupt request packets not coming from the ioapic. 0 linten_intr. local interrupt enable intr. 1 = mt[3] is set in hypertransport link intr interrupt request packets not coming from the ioapic. bits description 7 mpirq. multi-processor irq mode. this bit is combined with the mask bits of ioapic redirection table entries 23 through 20 and used to specify if the gpio[31:28] inputs are mapped to drive the pirq[a,b,c,d]_l pins low, respectively (gpio28 to pirqa_l, etc.). for each of these four pins: if (mpirq & mask[23:20] & ~gpio[31:28]) then pirq[a,b,c,d]_l = 0; else pirq[a,b,c,d]_l = z; // high impedance the polarity of gpio[31:28], in the above equation, is as seen on the external pins; the polarity is not altered the programming of devb:3x[df:dc]. the four gpio pins may all be mapped to pirqd_l, as speci ed by devb:0x47[alltod]. 6 must be low. this bit is required to be low at all times; if it is high then unde ned behavior results. 5 must be low. this bit is required to be low at all times; if it is high then unde ned behavior results. 4:3 must be low. this bit is required to be low at all times; if it is high then unde ned behavior results. 2 reserved. 158 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information miscellanous register devb:0x4c default: 0000h. attribute: read-write. miscellanous register devb:0x4e default: c000h. attribute: read-write. pci prefetching control 0 devb:0x50 default: 0000 0000h. attribute: see below. 1 must be low. this bit is required to be low at all times; if it is high then unde ned behavior results. 0 apicen. ioapic enable. 0=accesses to the ioapic memory mapped register space are ignored; also, the dual 8259 pic may generate interrupts through hypertransport messages. 1=the ioapic is enabled; the pic does not directly generate interrupt requests through hypertransport messages (although intr goes through the ioapic redirection table, which may result in an interrupt request hypertransport message). bits description 15:13 reserved. 12 must be low. this bit is required to be low at all times; if it is high then unde ned behavior results. 11 must be low. this bit is required to be low at all times; if it is high then unde ned behavior results. 10 must be low. this bit is required to be low at all times; if it is high then unde ned behavior results. 9 must be low. this bit is required to be low at all times; if it is high then unde ned behavior results. 8 must be low. this bit is required to be low at all times; if it is high then unde ned behavior results. 7:0 must be low. these bits are required to be low at all times; if they are high then unde ned behavior results. bits description 15:0 must be low. these bits are required to be set low during initialization; if any bits are high then unde ned behavior results. bits description 31:24 reserved. 23:21 [dpdm7, dpdh7, pfen7_l] . these bits apply to the preq_l/pgnt_l pair. see bits 2:0. 20:18 [dpdm6, dpdh6, pfen6_l]. these bits apply to the req_l[6]/gnt_l[6] pair. see bits 2:0. 17:15 [dpdm5, dpdh5, pfen5_l]. these bits apply to the req_l[5]/gnt_l[5] pair. see bits 2:0. 14:12 [dpdm4, dpdh4, pfen4_l]. these bits apply to the req_l[4]/gnt_l[4] pair. see bits 2:0. 11:9 [dpdm3, dpdh3, pfen3_l]. these bits apply to the req_l[3]/gnt_l[3] pair. see bits 2:0. 8:6 [dpdm2, dpdh2, pfen2_l]. these bits apply to the req_l[2]/gnt_l[2] pair. see bits 2:0. bits description (continued) chapter 4 registers 159 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information pci prefetching control 1 devb:0x54 when prefetching is enabled by devb:0x50[pfenx_l] (x=0...7) and a burst read request occurs, then the ic requests data starting from the request address up to the end of the cacheline, when the request address is smaller or equal to devb:0x44[tom] or when devb:0x44[allpf] = 1. when prefetching is disabled and the request address is smaller or equal to devb:0x44[tom] or when devb:0x44[allpf] = 1 then the ic requests two double-words of data. otherwise it requests one double-word of data (with the correct byte enables). prefetching of a second, third or fourth cacheline as enabled by ipf_mr, ipf_mrl, ipf_mrm only occurs when all of the following conditions are valid. 1. more than 1 internal pci response buffer is available. 2. at least 1 internal hypertransport command buffer is available. 3. the request address is smaller or equal to devb:0x44[tom] or devb:0x44[allpf] = 1. 5:3 [dpdm1, dpdh1, pfen1_l]. these bits apply to the req_l[1]/gnt_l[1] pair. see bits 2:0. 2 dpdm0. discard prefetch data upon upstream or peer to peer transaction . read-write.this bit applies to the req_l[0]/gnt_l[0] pair. 1 = when there is a transaction from any preq_l/req_l[6:1] input which targets anothers device on the pci (peer-to-peer), or a transaction from the same master (request from req_l[0]) targetting a different location (either to the host or peer-to-peer), no further prefetching occurs and any prefetch data not yet transferred is discarded, except for one doubleword (the next one to transfer). discarding only happens if this transaction is not nished with a master abort. 0 = master requests from preq_l/req_l[6:0] inputs do not affect prefetching. 1 dpdh0. discard prefetch data upon host request. read-write. this bit applies to the req_l[0]/ gnt_l[0] pair. 1 = when there is a host request to the pci bridge which is executed on the pci bus, no further prefetching occurs and any prefetch data not yet transferred is discarded, except for one doubleword (the next one to transfer). 0 = host requests to the pci bridge do not effect prefetching. note: programming of this bit may very based on platform requirements. dpdh is typically programmed low by system bios. the system bios may set this bit to protect against stale prefetch-data scenarios, as described in the pci speci cation, revision 2.3, section 3.10, point 6; scenarios similar to this have been observed, albeit rarely. however, if the pci bus includes a device that is accessed frequently as a target, then setting this bit may result in reduced memory read bandwith. 0 pfen0_l. prefetch enable (active low) 0 for busmaster burst read requests. read-write. this bit applies to the req_l[0]/gnt_l[0] pair. 1 = prefetching is not enabled. when prefetching is not enabled and a non-burst read request occurs, then the ic requests one double-word of data from the host. when prefetching is not enabled and a burst read request occurs, then the ic requests two double-words of data from the host. 0 = prefetching is enabled. when prefetching is enabled and a non-burst read request occurs, then the ic requests one double-word of data from the host. when prefetching is enabled and a burst read request occurs, then the ic requests prefetch data as controlled by devb:0x50. 160 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information prefetching of the ?st, second, third or fourth cacheline as enabled by cpfen_mr, cpfen_mrl, cpfen_mrm only occurs when all of the following conditions are valid. 1. at least 1 internal pci response buffer is available. 2. at least 1 internal hypertransport command buffer is available. the request address is smaller or equal to devb:0x44[tom] or devb:0x44[allpf] = 1. default: 0000 0185h. attribute: see below. bits description 31:16 reserved. 17 reserved. 16 reserved. 15:12 pddtv. prefetch data discard timer value. read-write. the discard timer for prefetch data expires after pddtv*2 6 + 64 clock cycles. with the expiration of this timer all prefetch data is discarded. (revision c1 and later) 11 reserved. 10:9 bllimit. burst length limit. . read-write. these bits specify how many cachelines are allowed to be continuesly transfered to/from the external master. these bits apply to read and write bursts. 00 = no limitation 01 = 4 cachelines 10 = 8 cachelines 11 = 12 cachelines if the burst length counter exceed these limits then the ic disconnects the transfer (even if in the read case the next cacheline is available). any prefetch operation stays unaffected. 8:6 [cpfen_mrm, ipf_mrm]. these bits apply to memory read multiple requests. see bits 2:0. 5:3 [cpfen_mrl, ipf_mrl]. these bits apply to memory read line requests. see bits 2:0. 2 cpfen_mr. continuous prefetch enable for memory read request. read-write. 1 = one or more cachelines (up to three) of prefetch data is requested when a cacheline starts to be transfered to the external master on the pci bus. more cachelines are only requested if the ipf count is not yet satis ed. 0 = no cacheline of prefetch data is requested when a cacheline is transferred to the master. 1:0 ipf_mr. initial prefetch for memory read request. read-write. these bits specify how many cachelines of prefetch data are requested upon an initial burst read request. this does not apply to any burst read request that is retried because of a previous target disconnect. 00 = 1 cacheline 01 = 2 cachelines 10 = 3 cachelines 11 = 4 cachelines chapter 4 registers 161 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information debug control 1 devb:0x58 default: ???? ????h. attribute: see below. debug control 2 devb:0x5c default: 0000 0000h. attribute: see below. device and subsystem id read-write register devb:0x70 default: 0000 0000h. attribute: read-write. non volatile ram base address register devb:0x74 default: de00h. attribute: see below. bits description 31 must be low . read-write. these bits are required to be low at all times. setting this bit can result in an unde ned behaviour. 30:8 reserved. read-only. reading these bits provides unde ned values. 7:0 reserved. read-only. reading these bits provides unde ned values. bits description 31:3 reserved. 2 must be low . read-write. this bit is required to be low at all times. setting this bit may result in an unde ned behaviour. 1 must be low . read-write. this bit is required to be low at all times. setting this bit may result in an unde ned behaviour. 0 must be low . read-write. this bit is required to be low at all times. setting this bit may result in an unde ned behaviour. bits description 31:16 ssid. subsystem id. the value placed in this register is visible devb:0x2c[31:16]. 15:0 ssvendorid. subsystem vendor id. the value placed in this register is visible devb:0x2c[15:0]. bits description 15:8 iobase. i/o space base address. read-write. this eld speci es bits[15:8] the i/o address space from which the 256-byte non-volatile ram may be accessed. the non-volatile ram is powered by the vdd_coreal plane; if vdd_coreal becomes invalid, then the contents of the non volatile ram become invalid. 7:1 read-only. these bits are xed to 7 b 000_0000. 0 nvramen. non-volatile ram enable. read-write. 1=accesses to the 256 byte i/o space speci ed devb:0x74[iobase] is claimed by non-volatile ram. 0= nonvolatile ram doesn t claim cycles. 162 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information bios access control registers devb:0x80, devb:0x84, and devb:0x88 default: 0000 0000h (for each). attribute: read-write. these registers consists of 24 4-bit registers called oar (open at reset) locks. each 4-bit register applies to a sector of the bios in the 5 megabyte bios range at the top of the 4-gigabyte address space as follows: devb:0x84 and devb:0x80 contain 16 four-bit lock registers, called oarx where x ranges across [f:0]; each four-bit register controls a 64kbyte address range at the top megabyte of memory as follows: [fffx_ffffh:fffx_0000h]. devb:0x88 contains 8 four-bit lock registers, called oarx where x ranges as [e, c, a, 8, 6, 4, 2, 0]; each four-bit register controls an 8kbyte address range as follows: [ffbf_(x+1)fffh:ffbf_x000h]. accesses to bios space in the low megabyte (between 000c_0000h and 000f_ffffh) are mapped to the top megabyte (between fffc_0000h and ffff_ffffh) on the lpc bus; the oar locks for these apply to these accesses based on the remapped address at the top megabyte. note: there is an additional oar lock speci?d in devb:0x8c. note: oar locks only apply to bios address space; if there is an access to an oar lock address range that is not in bios address space as de?ed by devb:0x43, then the oar lock register is ignored. note: the oar locks only apply to the bios address space on the lpc bus; if devb:3x48[pcibios] = 1, then they are ignored. as de?ed below, access to bios space can be limited to when the host is in system management mode (smm). hypertransport technology system management messages are sent that specify when the host is in smm. table 48. oarx lock locations register bits 31:28 bits 27:24 bits 23:20 bits 19:16 bits 15:12 bits 11:8 bits 7:4 bits 3:0 devb:0x88: oare oarc oara oar8 oar6 oar4 oar2 oar0 devb:0x84: oarf oare oard oarc oarb oara oar9 oar8 devb:0x80: oar7 oar6 oar5 oar4 oar3 oar2 oar1 oar0 table 49. oarx lock bit descriptions bits description oarx[3] fllock. full access to rd/wrlock lock. read; write 1 only. this bit can only be set high by software; it is cleared by reset_l. 0=read-write access to rdlock and wrlock enabled. 1=write access to rdlock and wrlock disabled (whether the system is in smm mode or not). oarx[2] sllock. smm access to rd/wrlock lock. read; write 1 only. this bit can only be set high by software; it is cleared by reset_l. 0=read-write access to rdlock and wrlock enabled (if fllock=0). 1=write access to rdlock and wrlock only enabled in smm mode (if fllock=0). oarx[1] wrlock. bios sector x write lock. read; write if enabled by sllock and fllock. 0=write access to bios sector x enabled (if devb:0x40[rwr]=1). 1=write access to bios sector x disabled. oarx[0] rdlock. bios sector x read lock. read; write if enabled by sllock and fllock. 0=read access to bios sector x enabled. 1=read access to bios sector x disabled. chapter 4 registers 163 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information oar control register devb:0x8c default: 00h. attribute: see below. read-write register devb:0x90 default: 0000h. attribute: read-write. high precision event timer base address register devb:0xa0 default: 0000 0000h. attribute: see below. bits description 7:6 reserved. 5 smiack. system in locked state. read-only. 1=the last smi mode special cycle received by the ic indicated that the host is in system management mode. 0=the last smi mode special cycle received by the ic indicated that the host is in not system management mode. 4 lklock. smm access to the rom access registers lock. read, write 1 only. this bit can only be set high by software; it is cleared by reset_l. 0=write access to devb:0x80, devb:084, devb:0x88, devb:0x8c and devb:0x43 enabled. 1=write access to devb:0x80, devb:084, devb:0x88, devb:0x8c and devb:0x43 only enabled in smm mode (see devb:0x80 or the de nition of when the system is in smm mode). 3:0 oar_rob. oar locks for rest of bios space. read-write. these four bits are de ned identically to the oar registers in devb:0x80 and devb:0x84. they apply to the bios rom space across [ffef_ffffh:ffc0_0000h] (if the space is speci ed by devb:0x43 to be bios). bits description 15:0 read-write. these bits are read-write accessible through software; they control no hardware. bits description 31:10 hpetbar. high precision event timer base address. read-write. these bits are used in the memory space for decoding the memory mapped high precision event timer registers. there is a maximum of 1 kbyte for this base address. 9:1 read-only. these bits are xed to 0. 0 hpeten. high precision event timer enable. read-write. if set it means that the hpet address decoding through devb:0xa0 is enabled. 164 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information watchdog timer base address register devb:0xa8 default: 0000 0002h. attribute: see below. 4.4 legacy registers 4.4.1 miscellaneous fixed i/o space registers these registers are in i/o space, at ?ed addresses. see section 4.1.2 on page 136 for a description of the register naming convention. at compatibility register port61 fixed i/o space; offset: 61h. default: 00h. attribute: see below. bits description 31:5 wdtbar. watchdog timer base address. read-write. these bits are used in the memory space for decoding the memory mapped watchdog timer registers. there is a maximum of 32 bytes for this base address. 4:3 read-only. these bits are xed to 0. 2 wdtsilent. watchdog timer silent mode. read-write. when set the watchdog timer does not cause any action as speci ed by wdt00[wact] upon expiring. when cleared the watchdog timer silent mode is disabled. 1 wdthalt. watchdog timer halt. read-write . when set the watchdog timer goes into the idle state and its functionality is disabled. when cleared the watchdog timer functionality is enabled. 0 wdten. watchdog timer enable. read-write. when set the watchdog timer address decoding as controlled by devb:0xa8[wdtbar] is enabled. bits description 7 serr. serr_l latch. read-only. this bit is set high when serr_l is asserted and stays high until cleared by port61[clrserr]. the state of this bit is combined with rtc70[nmidis] and port61[iochk] to generate nmi interrupts. 6 iochk. iochk_l latch. read-only. this bit is set high when the serial irq signal iochk_l is asserted or if there is a sync with error message received on the lpc bus; it stays high until cleared by port61[clriochk]. the state of this bit is combined with rtc70[nmidis] and port61[serr] to generate nmi interrupts. 5 tmr2. programmable interval timer, timer number 2 output. read-only. this bit provides the current state of the output signal from legacy pit timer number 2. 4 rshclk. refresh clock. read-only. this bit toggles state at intervals speci ed by pit timer 1 (normally, every 15 microseconds). chapter 4 registers 165 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information system control register port92 fixed i/o space; offset: 92h. default: 00h. attribute: see below. fixed i/o ports f0 and f1 and the ferr_l and ignne_l logic portf0 and portf1 fixed i/o space; offset: f0h and f1h. default: 00h. attribute: see below. ferr_l is used to control ignne_l and generate irq13 to the pic and ioapic. the following diagram shows the logic. ferr_clr_l is asserted by (1) an i/o write to f0h, (2) an i/o write to f1h, (3) any processor reset command, and (4) pwrok reset; when any of these are active, ferr_clr_l goes low. 3 clriochk. clear port61[iochk]. read-write. 1=bit[6] of this register, iochk, is asynchronously cleared. 0=port61[iochk] can be set high. 2 clrserr. clear port61[serr]. read-write. 1=bit[7] of this register, serr, is asynchronously cleared. 0=port61[serr] can be set high. 1 spkren. speaker enable. read-write. 1=the output of pit timer number 2 drives the spkr pin. 0=spkr is held low. 0 tmr2en. programmable interval timer, timer number 2 enable. read-write. 1=pit timer 2 is enabled to count. 0=pit timer 2 is halted. bits description 7:2 reserved. 1 a20en. processor address bit 20 enable. write-only; reads provide the current state of the virtual a20m_l hypertransport link wire rather than the state of the bit. the value written to this bit is ored with the ka20g bit from the keyboard controller before being sent as a hypertransport technology message. in order for this register to control a20m_l, ka20g must be low. 0 initcpu. generate processor initialization command. read-write. when this bit is low and then written to a high, the ic sends an init message. this bit must be written to a low again before another init message can be sent. note: use of this bit is enabled by devb:0x41[p92fr]. 166 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information figure 31. ferr_l and ignne_l logic level sensitive irq select register port4d0 fixed i/o space; offset: 4d0h and 4d1h. default: 0000h. attribute: read-write. bits description 15:0 lirq. level sensitive irqs. each of these 16 bits controls whether a corresponding irq line that enters the legacy pic is edge sensitive (if the bit is low) or level sensitive (if it is high). edge sensitive interrupts must enter the pic such that the rising edge generates the interrupt and level sensitive interrupts must enter the pic as active low; see section 3.4.2.1 on page 41 for details about how the interrupts are mapped to the pic. the bit numbers correspond directly to the irq numbers (e.g., bit[12] controls irq12). bits[0 and 2] are reserved (irq0 is always edge sensitive and irq2 does not exist). d set q gnd clk ff ignne_l d set q gnd clk ff irq13 ferr_clr_l ferr_l chapter 4 registers 167 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information system reset register portcf9 notes: 1. this register is enabled by devb:3x41[pcf9en]. 2. this register may be accessed only as a byte operation; 16- or 32-bit accesses to port cf8h are ignored by this register. fixed i/o space; offset: cf9h. default: 00h. attribute: see below. 4.4.2 legacy dma controller (dmac) registers the legacy dma controller (dmac) in the ic supports the features required by the lpc i/f speci?ation revision 1.0, which are a subset of legacy dma controllers. single, demand, verify, and increment modes are supported. block, decrement, cascade modes are not supported. also, memory-to-memory transfers and external eops (end of process) are not supported. there are 7 supported dma channels. channels 0-3 support 8-bit transfers and channels 5-7 support 16-bit transfers. there is no support for 32-bit dma transfers. lpc master device requests are made using channel 4. although not all registers in legacy dma controllers are supported, the i/o address locations for the unsupported registers is consistent with legacy logic. the implemented dmac registers are listed in the following table. bits description 7:4 reserved. 3 fullrst. full reset. read-write. 1=full resets require the ic to place the system in the soff state for 3 to 5 seconds; full resets occurs whenever (1) rstcmd and sysrst are both written high, (2) an ac power fail is detected (pwrok goes low without the appropriate command), or (3) when pm46[2ndto_sts] is set while devb:3x48[no_reboot]=0. 0=full resets do not transition the system to soff; only the reset signals are asserted. 2 rstcmd. reset command. write-only; always reads as a zero. when this bit is written with a 1, a reset is generated as speci ed by bits[3,1] of this register (bits[3,1] are observed in their state when rstcmd is written to a 1; their previous value does not matter). 1 sysrst. system reset. read-write. this bit speci es whether a full system reset or a processor init is generated when portcf9[rstcmd] is written to a 1. 1=full system reset with reset_l and ldtrst_l asserted for about 1.8 milliseconds. 0=init hypertransport message is sent. 0 reserved. 168 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information note that not all bits in the command and mode registers of legacy dma controllers are used in the ic s dma controller. the bit usage for these registers are as follows. note: dma channel 4 is hardwired into cascade mode; however is obsolete for all other channels. for debug purposes writes to the dma page registers at 0x80 to 0x87 show up on pci and lpc. it is expected that no external device claims these cycles nor responds to these cycles. table 50. dma controller register summary name size number comments base address registers 16 bits 8 1 for each channel (0-7) (see note) base word count registers 16 bits 8 1 for each channel (0-7) (see note) current address registers 16 bits 8 1 for each channel (0-7) (see note) current word count registers 16 bits 8 1 for each channel (0-7) (see note) status registers 8 bits 2 1 for master and 1 for slave dmac command registers 1 bit 2 1 for master and 1 for slave dmac mode registers 5 bits 8 1 for each channel (0-7) (see note) mask registers 4 bits 2 1 for master and 1 for slave dmac note: although channel 4 base and current registers exist for compatibility, they are not used. table 51. dma command register bits (master and slave dmac) bit 8237 function dmac function of the ic 7 dack sense obsolete 6 dreq sense obsolete 5 late/extended write obsolete 4 fixed/rotating priority obsolete (always xed priority) 3 normal/compressed timing obsolete 2 controller enable/disable controller enable/disable 1 ch0 address hold enable/disable obsolete 0 memory-to-memory enable/disable obsolete table 52. dma mode register bits (master and slave dmac) bit 8237 function dmac function of the ic 7:6 00b demand mode select 01b single mode select 10b block mode select 11b cascade mode select 00b demand mode select 01b single mode select 10b obsolete 11b obsolete 5 address increment/decrement select obsolete (always increment) 4 auto initialization enable/disable auto initialization enable/disable 3:2 00b verify transfer 01b write transfer 10b read transfer 11b illegal 00b verify transfer 01b write transfer 10b read transfer 11b illegal 1:0 channel select channel select chapter 4 registers 169 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 4.4.3 legacy programmable interval timer (pit) registers these timers are halted from counting, if enabled to do so in devb:3x4c[pit_dis], when prdy is asserted. here are the ports used to access the legacy pit: table 53. pit register summary offset access port 40h write counter 0 write access port read counter 0 read access port 41h write counter 1 access port read counter 1 read access port 42h write counter 2 access port read counter 2 read access port 43h write control byte read not supported 170 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information pit control byte register port43 fixed i/o space; offset: 43h. default: 00h. attribute: write-only. 4.4.4 legacy programmable interrupt controller (pic) the legacy dual-8259 programmable interrupt controller (pic) includes a master, which is accessed through ports 20h and 21h and controls irq[7:0], and a slave, which is accessed through ports a0h and a1h and controls irq[15:8]. here are all the pic registers. bits description 7:6 sc[1:0]. select counter. speci es the counter that the command applies to as follows: 00b counter 0. 01b counter 1. 10b counter 2. 11b read back command. 5:4 rw[1:0]. read-write command. speci es the read-write command as follows: 00b counter latch command. 01b read-write least signi cant byte only. 10b read-write most signi cant byte only. 11b read-write least signi cant byte followed by most signi cant byte. 3:1 m[2:0]. counter mode. speci es the mode in which the counter selected by sc[1:0] operates as follows: 000b interrupt on terminal count. 001b hardware retriggerable one-shot (not supported). 010b rate generator. 011b square wave mode. 100b software triggered strobe. 101b hardware triggered (retriggerable) strobe (not supported). 110b when this value is written, 010b is stored in the register, rate generator mode. 111b when this value is written, 011b is stored in the register, square wave mode. 0 bcd. binary coded decimal. 1=counter speci ed by sc[1:0] operates in binary coded decimal. 0=counter speci ed by sc[1:0] operates in 16-bit binary mode. chapter 4 registers 171 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information d[4:3] above refers to bits[4:3] of the associated 8-bit data ?ld. normally, once icw1 is sent, icw2, icw3, and icw4 are sent in that order before any ocw registers are accessed. initialization command word 1 register icw1 fixed i/o space; offset: 20h for master and a0h for slave; data bit[4] must be high. attribute: write-only. initialization command word 2 register icw2 fixed i/o space; offset: 21h for master and a1h for slave. attribute: write-only. initialization command word 3 for master register icw3m fixed i/o space; offset: 21h. attribute: write-only. table 54. pic register summary offset access type register 20h (master), write-only; d[4]=1b initialization command word 1 (icw1) a0h (slave) write-only; d[4:3]=00b operation command word 2 (ocw2) read-write; d[4:3]=01b operation command word 3 (ocw3) 21h (master), write-only initialization command word 2 (icw2) a1h (slave) write-only initialization command word 3 (icw3) write-only initialization command word 4 (icw4) read-write operation command word 1 (ocw1) bits description 7:5 a[7:5]. interrupt vector address. these bits are not implemented. 4 this should always be high. 3 ltim. level triggered mode. this bit is not implemented; port4d0 controls this function instead. 2 adi. call address interval. this bit is not implemented. 1 sngl. single mode. this bit must be programmed low to indicate cascade mode. 0 ic4. icw4 needed. this bit must be programmed high. bits description 7:3 t[7:3]. interrupt vector table base address bits[7:3] . 2:0 a[10:8]. obsolete. these bits must be programmed low. bits description 7:0 slaves[7:0]. these bits must always be programmed to 04h. 172 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information initialization command word 3 for slave register icw3s fixed i/o space; offset: a1h. attribute: write-only. initialization command word 4 register icw4 fixed i/o space; offset: 21h for master and a1h for slave. attribute: write-only. operation command word 1 register ocw1 fixed i/o space; offset: 21h for master and a1h for slave. attribute: write-only. operation command word 2 register ocw2 fixed i/o space; offset: 20h for master and a0h for slave; data bits[4:3] must be 00b. attribute: write-only. bits description 7:3 reserved (must be programmed to all zeros). 2:0 id[2:0]. these bits must always be programmed to 02h. bits description 7:5 reserved (must be programmed all zeros) 4 sfnm. special fully nested mode. this bit is normally programmed low. 3:2 buff and ms. these two are normally programmed to 00b for non-buffered mode. 1 aeoi. auto eoi. this bit is ignored; the ic only operates in normal eoi mode (this bit low). 0 upm. x86 mode. this bit is ignored; the ic only operates in x86 mode (this bit high). bits description 7:0 mask[7:0]. interrupt mask. 1=interrupt is masked. masking irq2 on the master interrupt controller masks all slave-controller interrupts. bits description 7:5 r (bit 7), sl (bit 6), and eoi (bit 5). these are decoded as: r, sl, eoi function r, sl, eoi function 000b 1 rotate in auto eoi mode clear. 100b 1 rotate in auto eoi mode set 001b non-speci c eoi mode. 101b rotate on non-speci c eoi command 010b no operation. 110b 2 set priority command 011b speci c eoi command. 111b 2 rotate on speci c eoi command notes: 1. values 000b and 100b are not supported. 2. values 110b and 111b use the irlevel ?ld. 4:3 reserved (must be programmed all zeros) 2:0 irlevel. interrupt request level. speci es the interrupt request level to be acted upon. chapter 4 registers 173 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information operation command word 3 register ocw3 fixed i/o space; offset: 20h for master and a0h for slave; data bits[4:3] must be 01b. attribute: write-only. 4.4.5 ioapic registers the ioapic register set for the 24 ioapic interrupts supported by the ic is indexed through two ?ed-location, memory-mapped ports: fec0_0000h, which provides the 8-bit index register, and fec0_0010h, which provides the 32-bit data port. writes to the 32-bit data port at fec0_0010h must be 32-bit, aligned accesses; other than 32-bit writes result in unde?ed behavior. reads provide all four bytes regardless of the byte enables. the access to these memory locations can be disabled using devb:0x4b[apicen]. the index register selects one of the following: bits description 7 must be programmed low. 6:5 esmm (bit 6) and smm (bit 5). special mask mode . these are decoded as: [esmm, smm] = 0xbno action. [esmm, smm] = 10breset special mask mode. [esmm, smm] = 11bset special mask mode. 4:3 01b 2 p. poll command. 1=poll enabled; next i/o read of the interrupt controller treated like an interrupt acknowledge cycle. 1:0 rr (bit 1) and ris (bit 0). read register command. these are decoded as: [rr,ris] = 0xb no action. [rr,ris] = 10b read in-request (ir) register. [rr,ris] = 11b read is register. index description attribute default 00h apic id register. the id is in bits[27:24]. all other bits are reserved. read-write 0000 0000h 01h ioapic version register. read-only 0017 0011h 02h ioapic arbitration id register. the id is in bits[27:24]. all other bits are reserved. read-only 0000 0000h 10h-3fh redirection registers. each of the 24 redirection registers utilizes two of these indexes. bits[63:32] are accessed through the odd indexes and bits[31:0] are accessed through the even indexes. read-write 0000 0000 0001 0000h 40h-ffh reserved. 174 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information the redirection registers are de?ed as follows: normally all level triggered interrupts are programmed active low and all edge triggered interrupts are programmed active high. normally redirection register 0 (intr) is programmed to be active high, edge triggered. the ic also provides alternative means for con?uring the ioapic as required by the hypertransport speci?ation. this access method is realized by using deva:0xf0 which contains the index register and deva:0xf4 which is the dataport. the access to these con?uration registers is always possible independent of the state of the devb:0x4b[apicen] bit. the index register selects one of the following: bits description 63:56 destination. in physical mode, bits[59:56] specify the apic id of the target processor. in logical mode bits[63:56] specify a set of processors. 55:17 reserved. 16 interrupt mask. 1=interrupt is masked. 15 trigger mode. 0=edge sensitive. 1=level sensitive. note: this bit is ignored for delivery modes of smi, nmi, init, and extint, which are always treated as edge sensitive. 14 irr. interrupt request receipt. set by hardware; cleared by hardware. this bit is not de ned for edge-triggered interrupts. for level-triggered interrupts, this bit is set by the hardware after an interrupt is detected. it is cleared by receipt of eoi with the vector speci ed in bits[7:0]. 13 polarity. 0=active high. 1=active low. 12 delivery status. 0=idle. 1=interrupt message pending. 11 destination mode. 0=physical mode. 1=logical mode. 10:8 delivery mode. 000b= xed. 001b=lowest priority. 010b=smi. 011b=reserved. 100b=nmi. 101=init. 110b=reserved. 111b=extint. 7:0 interrupt vector. index description attribute default 00h reserved. read-only 0000 0000h 01h last interrupt . the number of the last interrupt is stored in bits[23:16]. all other bits are reserved. read-only 0017 0000h 02h-09h reserved. read-only 0000 0000h 10h-3fh interrupt de nition registers . each of the 24 registers utilizes two of these indexes. bits[63:32] are accessed through the odd indexes and bits[31:0] are accessed through the even indexes. read-write 0000 0000 f800 0001h 40h-ffh reserved. read-only 0000 0000h chapter 4 registers 175 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the interrupt de?ition registers are de?ed as follows: 4.4.6 watchdog timer registers the watchdog timer registers are non-enumerable memory mapped i/o registers. the base address is controlled by devb:0xa8. all register can be accessed by 32-bit memory accesses. bits description 63 wait for eoi. read-write. this bit is set by hardware when an interrupt request is sent and cleared by hardware when the eoi is returned. software may write a 1 to clear this register without an eoi so that the device can send another interrupt. writing 0 has no effect. this bit is not de ned if rqeoi is clear. 62 passpw. read-write. 1= the hypertransport interrupt message will have the pass pw bit set and is allowed to pass other posted requests. 0= the pass pw bit in the interrupt message will be clear. 61:56 reserved. 55:32 intrinfo[55:32]. read-write. these bits contain the interrupt information bits 55:32 which are send in the interrupt message. 31:24 intrinfo[31:24]. read-write. these bits contain the interrupt information bits 31:24 which are send in the interrupt message. should be programmed to f8h for compliance with earlier hypertransport technology implementations. 23:6 intrinfo[23:6]. read-write. these bits contain the interrupt information bits 23:6 which are send in the interrupt message. 5 rqeoi. request eoi. read-write. when set, after each interrupt request is sent the device waits for an eoi (or software clears the wait for eoi bit) before sending another interrupt. 4:2 message type. read-write. speci es the type of interrupt. see hypertransport technology speci cation 1.02 for valid settings. 1 polarity. read-write. this bit is only valid for external interrupt sources (e.g., pins). 1= the interrupt signal is active-low. 0= the interrupt signal is active-high. 0 mask. read-write. 1= interrupt masked, no interrupt is sent from this source (default). 0= interrupt can be sent. table 55. watchdog timer registers address mnemonic name default 00h wdt00 watchdog timer control/status register 0000_0008h 08h wdt08 watchdog timer count register 0000_0000h 176registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information watchdog timer control/status register wdt00 default: 0000 0008h. attribute: see below. watchdog timer count register wdt08 default: 0000 0000h. attribute: see below. 4.4.7 high precision event timer registers the hpet registers are non-enumerable memory mapped i/o registers. the base address is controlled by devb:0xa0. all registers can be accessed by 32 bit memory accesses. bits description 31:8 read-only. 7 wtrig. watchdog trigger . read-write. setting this bit triggers the watchdog timer to start a new count interval, counting down from the value that was last written to the watchdog count register. this bit always reads as zero. setting this bit has no effect when devb:0xa8[wdthalt] is set or rstop is cleared. 6:4 read-only. 3 wda_alias. watchdog disable alias . read-only. this bit re ects the state of the watchdog timer hardware and is an alias of devb:0xa8[wdthalt]. 1 = watchdog timer functionality disabled. 0=watchdog timer functionality enabled. 2 wact. watchdog action . read-write. this bit determines the action to be taken when the watchdog timer expires. 0 = system reset; 1 = system power off. 1 wfir. when set, the watchdog timer expired and caused the current restart .read-write. this bit is cleared for any restart that is not caused by the watchdog timer ring. if the watchdog action bit is set to 1 (system power off) and the watchdog timer res, forcing a shutdown, the bit will be cleared on the next power up. 0 rstop. read-write. this bit is used to control or indicate whether the watchdog timer is in the running or stopped state. 1 = watchdog timer is in the running state. 0 = watchdog timer is in the stopped state. if the watchdog timer is in the stopped state and a 1 is written to bit 0, the watchdog timer moves to the running state but a count interval is not started until a 1 is written to bit 7. if the watchdog timer is in the running state, writing a 1 to bit 0 has no effect. bits description 31:16 read-only. 15:0 wcd. watchdog count data . read-write. this de nes the countdown time for the counter in seconds. reading this register results in the current counter value. writing to the register has no effect until a one is written to the watchdog trigger bit of the watchdog control/status register. all bits have to be written by one access. chapter 4 registers 177 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information hpet general capabilities and id register hpet00 default: 0429 b17f 1022_82xxh attribute: read-only. hpet general con g register hpet10 default: 0000_0000_0000_0000h attribute: see below. table 56. hpet registers address mnemonic name default 00h hpet00 hpet general capabilities and id register 0429_b17f_1022_82xxh 10h hpet10 hpet general con g register 0000_0000_0000_0000h 20h hpet20 hpet general interrupt status register 0000_0000_0000_0000h f0h hpetf0 hpet main counter register 0000_0000_0000_0000h 100h hpet100 hpe timer 0 con guration and capabilities register 000f_defa_0000_0010h 108h hpet108 hpe timer 0 compare register 0000_0000_ffff_ffffh 120h hpet120 hpe timer 1 con guration and capabilities register 000f_defa_0000_0000h 128h hpet128 hpe timer 1 compare register 0000_0000_ffff_ffffh 140h hpet140 hpe timer 2 con guration and capabilities register 000f_defa_0000_0000h 148h hpet148 hpe timer 2 compare register 0000_0000_ffff_ffffh bits description 63:32 period. main counter clock period in femtoseconds . 31:16 vendid. vendor id . hardwired to 1022h (amd). 15 legsup. hardwired to 1b to ag that legacy interrupt routing is supported. 14 reserved. hardwired to 0b. 13 size. hardwired to 0b to ag 32 bit main counter. 12:8 numb. hardwired to 010b means 3 implemented comparators. 7:0 revid. hardware revision id . the value of this register is revision-dependent. bits description 63:2 reserved. read-only. hardwired to 0h. 1 lien. legacy irq routing enable .read-write. 0: use programmed value for irq routing 1: c0 delivers to irq0/intin2 instead of pit, c1 delivers to irq8/intin8 instead of rtc periodic timer interrupt. rtc alarm still delivers to sci. 0 gien. global interrupt enable . read-write. this bus must be set to enable any of the timers to generate interrupts. 1: allow counter to run, allow compare interrupts if enabled 0: halt counter, disable all compare interrupts 178 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information hpet general interrupt status register hpet20 default: 0000_0000_0000_0000h attribute: see below. hpet main counter register hpetf0 default: 0000_0000_0000_0000h attribute: see below. bits description 63:3 reserved. read-only. these bits are hardwired to 0. 2 c2_sts. comparator 2 interrupt active . read-write. if set to level-triggered mode, this bit defaults to 0. it is set by hardware if the corresponding interrupt is active. once the bit is set, it can be cleared by software writing a 1 to this bit. writes to 0 have no effect. if 1, a write to 0 doesn t clear this bit. in edge sensitive mode this bit has to be ignored by software, software should always writ ea0to this bit. 1 c1_sts. comparator 1 interrupt active . read-write. if set to level-triggered mode, this bit defaults to 0. it is set by hardware if the corresponding interrupt is active. once the bit is set, it can be cleared by software writing a 1 to this bit. writes to 0 have no effect. if 1, a write to 0 doesn t clear this bit. in edge sensitive mode this bit has to be ignored by software, software should always writ ea0to this bit. 0 c0_sts. comparator 0 interrupt active . read-write. if set to level-triggered mode, this bit defaults to 0. it is set by hardware if the corresponding interrupt is active. once the bit is set, it can be cleared by software writing a 1 to this bit. writes to 0 have no effect. if 1, a write to 0 doesn t clear this bit. in edge sensitive mode this bit has to be ignored by software, software should always writ ea0to this bit. bits description 63:32 reserved. read-only. these bits are hardwired to 0000_0000h. 31:0 mainc. read-write. these bits represent the content of the main counter. writes to this register should only be done while the counter is halted. chapter 4 registers 179 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information hpe timer 0 con guration and capabilities register hpet100 default: 000f_defa_0000_0010h attribute: see below. bits description 63:32 t0_route_cap. these bits indicate to which interrupts in the ioapic this timer s interrupt can be routed. each bit represents one interrupt. bit63 represents interrupt 31, bit 32 interrupt0. 63:52: read-only. hardwired to 000000000000b ioapic does not support interrupts 31 down to 20. 51:46: read-writeonce. these bits indicate if routing to intin19 down to intin14 of ioapic is allowed. 45: read-only. this bit is hardwired to 0b. routing to intin13 of ioapic is not allowed. 44:41: read-writeonce. these bits indicate if routing to intin12 down to intin9 of ioapic is allowed. 40: read-only. this bit is hardwired to 0b. routing to intin8 of ioapic is not allowed. 39:35: read-writeonce. these bits indicate if routing to intin7 down to intin3 of ioapic is allowed. 34: read-only. this bit is hardwired to 0b. routing to intin2 of ioapic is not allowed. 33: read-writeonce. this bit indicates if routing to intin1 of ioapic is allowed. 32: read-only. this bit is hardwired to 0b. routing to intin0 of ioapic is not allowed. 31:16 reserved. read-only. hardwired to 0000h. software should only write a 0000h to these bits. 15 t0_fsb_cap. read-only. this bit is hardwired to 0 to ag that no fsb routing is possible. 14 t0_fsb_en. read-only. this bit is hardwired to 0 to ag that no fsb routing is possible. 13:9 t0_int_route. read-write. this 5-bit eld de nes the routing to the ioapic. if the written value to this register doesn t match bits[63:32] of this register, then the most signi cant enabled interrupt is written instead. if hpet10[lien] or bit14 of this register is set then these bits have no effect. 8 m32. read-only. this bit is hardwired to 0b, because the timer doesn t support 64 bit mode and this bit is not needed. 7 reserved. read-only. hardwired to 0b. software should only write a 0b to this bit. 6 setval. read-write. timer 0 value set. software can set this bit to write the accumulator register of periodic timer. software should not set this bit, if this timer is not con gured as periodic timer. software has not clear this bit. it clears itself after writing hpet108. 5 size. read-only. hardwired to 0b to indicate that the timer is 32 bit only. 4 t0pcap. read-only. hardwired to 1b to ag, that this timer supports the periodic interrupt. 180 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information hpe timer 0 compare register hpet108 default: 0000_0000_ffff_ffffh attribute: see below. 3 t0pen. timer 0 periodic mode enable . read-write. if t0pcap is 0. this bit is always 0. writes have no effect. if t0pcap is 1, this bits enables the period mode of timer 0. 0 = disables timer 0 periodic mode 1 = enables timer 0 periodic mode 2 t0ien. timer 0 interrupt enable . read-write. this bit must be set to enable timer 0 to cause an interrupt when it times out. if this bit is 0, the timer can still count and generate the appropriate status bits, but does not cause an interrupt. 1 t0itype. timer 0 interrupt type .read-write. 0 = the timer interrupt is edge triggered. each new interrupt generates a new edge. 1 = the timer interrupt is level triggered. the interrupt is held active until the corresponding bit in the hpet20[c0_sts] register is cleared. if a new interrupt occurs before the interrupt is cleared, the interrupt remains active. 0 reserved. read-only. hardwired to 0. software should only write a 0 to this bit. bits description 63:32 reserved. read-only. these bits are hardwired to 0000_0000h. 31:0 t0comp. timer 0 comparator value .read-write. in non-periodic mode (hpet100[t0pen]=0) a write to this register sets the comparator value. reads to this register return the value of the comparator. when the main counter equals t0comp the corresponding interrupt is generated, if enabled. the value in this register does not change based on the generated interrupt. in periodic mode (hpet100[t0pen]=1) this register consists of two registers, one for saving the last software-written comparator value and one for the accumulator value. if hpet100[setval] is high a write to this address causes a write of this accumulator register, if hpet100[setval] is low a write to this address causes a change of the last software-written comparator value. the read value is the value of the accumulator register. when the main counter equals the accumulator register value, the last software-written comparator value is added to the accumulator, and the corresponding interrupt is generated, if enabled. bits description (continued) chapter 4 registers 181 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information hpe timer 1 con guration and capabilities register hpet120 default: 000f_defa_0000_0000h attribute: see below. bits description 63:32 t1_route_cap. these bits indicate to which interrupts in the ioapic this timer s interrupt can be routed. each bit represents one interrupt. bit63 represents interrupt 31, bit 32 interrupt0. 63:52: read-only. hardwired to 000000000000b ioapic doesn t support interrupts 31 down to 20. 51:46: read-writeonce. these bits indicate if routing to intin19 down to intin14 of ioapic is allowed. 45: read-only. this bit is hardwired to 0b. routing to intin13 of ioapic is not allowed. 44:41: read-writeonce. these bits indicate if routing to intin12 down to intin9 of ioapic is allowed. 40: read-only. this bit is hardwired to 0b. routing to intin8 of ioapic is not allowed. 39:35: read-writeonce. these bits indicate if routing to intin7 down to intin3 of ioapic is allowed. 34: read-only. this bit is hardwired to 0b. routing to intin2 of ioapic is not allowed 33: read-writeonce. this bit indicates if routing to intin1 of ioapic is allowed. 32: read-only. this bit is hardwired to 0b. routing to intin0 of ioapic is not allowed. 31:16 reserved. read-only. hardwired to 0000h. software should only write a 0000h to these bits. 15 t1_fsb_cap. read-only. this bit is hardwired to 0 to ag that no fsb routing is possible. 14 t1_fsb_en. read-only. this bit is hardwired to 0 to ag that no fsb routing is possible. 13:9 t1_int_route. read-write. this 5-bit eld de nes the routing to the ioapic. if the written value to this register doesn t match bits[63:32] of this register, then the most signi cant enabled interrupt is written instead. if hpet10[lien] or bit14 of this register is set then these bits have no effect. 8 m32. read-only. this bit is hardwired to 0, because the timer doesn t support 64 bit mode and this bit is not needed. 7 reserved. read-only. hardwired to 0. 6 setval. read-only. hardwired to 0. 5 size. read-only. hardwired to 0 to indicate that the timer is 32 bit only. 4 t1pcap. read-only. hardwired to 0 to ag, that this timer doesn t support the periodic interrupt. 3 t1pen. read-only. this bit is always 0. 2 t1ien. timer 1interrupt enable .read-write. this bit must be set to enable timer 0 to cause an interrupt when it times out. if this bit is 0, the timer can still count and generate the appropriate status bits, but does not cause an interrupt. 1 t1itype. timer 0 interrupt type. read-write. 0 = the timer interrupt is edge triggered. each new interrupt generates a new edge. 1 = the timer interrupt is level triggered. the interrupt is held active until the corresponding bit in the hpet20[c1_sts] register is cleared. if a new interrupt occurs before the interrupt is cleared, the interrupt remains active. 0 reserved. read-only. hardwired to 0. software should only write a 0 to this bit. 182 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information hpe timer 1 compare register hpet128 default: 0000_0000_ffff_ffffh attribute: see below. hpe timer 2 con guration and capabilities register hpet140 default: 000f_defa_0000_0000h attribute: see below. bits description 63:32 reserved. read-only. these bits are hardwired to 0. 31:0 t1comp. timer 1 comparator value . read-write. reads to this register return the value of the comparator. a write to this register sets the comparator value. when the main counter equals the value last written, the corresponding interrupt is generated, if enabled. the value in this register does not change based on the generated interrupt. bits description 63:32 t2_route_cap. these bits indicate to which interrupts in the ioapic this timer s interrupt can be routed. each bit represents one interrupt. bit63 represents interrupt 31, bit 32 interrupt0. 63:52: read-only. hardwired to 000000000000b ioapic doesn t support interrupts 31 down to 20. 51:46: read-writeonce. these bits indicate if routing to intin19 down to intin14 of ioapic is allowed. 45: read-only. this bit is hardwired to 0b. routing to intin13 of ioapic is not allowed. 44:41: read-writeonce. these bits indicate if routing to intin12 down to intin9 of ioapic is allowed. 40: read-only. this bit is hardwired to 0b. routing to intin8 of ioapic is not allowed. 39:35: read-writeonce. these bits indicate if routing to intin7 down to intin3 of ioapic is allowed. 34: read-only. this bit is hardwired to 0b. routing to intin2 of ioapic is not allowed 33: read-writeonce. this bit indicates if routing to intin1 of ioapic is allowed. 32: read-only. this bit is hardwired to 0b. routing to intin0 of ioapic is not allowed. 31:16 reserved. read-only. hardwired to 0000h. software should only write a 0000h to these bits. 15 t2_fsb_cap. read-only. this bit is hardwired to 0 to ag that no fsb routing is possible. 14 t2_fsb_en. read-only. this bit is hardwired to 0 to ag that no fsb routing is possible. 13:9 t2_int_route. read-write. this 5-bit eld de nes the routing to the ioapic. if the written value to this register doesn t match bits[63:32] of this register, then the most signi cant enabled interrupt is written instead. if hpet10[lien] or bit14 of this register is set then these bits have no effect. 8 m32. read-only. this bit is hardwired to 0, because the timer doesn t support 64 bit mode and this bit is not needed. 7 reserved. read-only. hardwired to 0. software should only write a 0 to this bit. 6 setval. read-only. hardwired to 0. 5 size. read-only. hardwired to 0 to indicate that the timer is 32 bit only. 4 t2pcap. read-only. hardwired to 0 to ag, that this timer doesn t support the periodic interrupt. chapter 4 registers 183 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information hpe timer 2 compare register hpet148 default: 0000_0000_ffff_ffffh attribute: see below. 4.4.8 real-time clock registers real-time clock legacy indexed address rtc70 note: rtc70[6:0] and rtc72 occupy the same physical register. after a write to rtc70, rtc72 reads back {0b, rtc70[6:0]}; after a write to rtc72, reads of rtc72 provide all 8 bits written. rtc70 and rtc72 are on the vdd_core power plane; they are not preserved in the str, std, soff, or moff states. i/o mapped (?ed); offset: 70h. default: 00. attribute: write-only. 3 t2pen. read-only. this bit is always 0. 2 t2ien. timer 1interrupt enable . read-write. this bit must be set to enable timer 0 to cause an interrupt when it times out. if this bit is 0, the timer can still count and generate the appropriate status bits, but does not cause an interrupt. 1 t2itype. timer 0 interrupt type .read-write. 0 = the timer interrupt is edge triggered. each new interrupt generates a new edge. 1 = the timer interrupt is level triggered. the interrupt is held active until the corresponding bit in the hpet20[c2_sts] register is cleared. if a new interrupt occurs before the interrupt is cleared, the interrupt remains active. 0 reserved. read-only. hardwired to 0. software should only write a 0 to this bit. bits description 63:32 reserved. read-only. these bits are hardwired to 0. 31:0 t2comp. timer 2 comparator value . read-write. reads to this register return the value of the comparator. a write to this register sets the comparator value. when the main counter equals the value last written, the corresponding interrupt is generated, if enabled. the value in this register does not change based on the generated interrupt. bits description 7 nmidis. nmi disable. 1=sources of nmis (from serial irq logic and serr_l pin) are disabled from being able to generate nmi interrupts. note: the state of this register is read accessible through devb:0x41[nmidis]. 6:0 rtcaddr. real-time clock address. speci es the address of the real-time clock cmos ram. the data port associated with this index is rtc71. only the lower 128 bytes of the cmos ram are accessible through rtc70 and rtc71. bits description (continued) 184 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information real-time clock legacy data port rtc71 i/o mapped (?ed); offset: 0071h. attribute: read-write. real-time clock 256-byte address and data port rtc72 and rtc73 i/o mapped (?ed); offsets: 0072h and 0073h. attribute: read-write. these two 8-bit ports are similar to rtc70 and rtc71. however, rtc72, the address register, provides the full eight bits needed to access all 256 bytes of cmos ram. rtc73, the data port, provides access to the cmos data indexed by rtc72. see rtc70 for details about reading rtc72. real-time clock alarm and century registers rtc offsets 7f:7d rtc indexed address space (indexed by rtc70); offsets: 7dh, 7eh, and 7fh. attribute: read-write. the day alarm, month alarm, and centenary value are stored in cmos ram indexed address space. bits[7:6] of the date alarm (offset 7dh) are reserved; writes to them have no effect and they always read back as zero. to place the rtc into 24-hour alarm mode, an invalid code must be written to bits[5:0] of the date alarm byte (any value other than 01h to 31h for bcd mode or 01h to f1h for hex mode). refer to the acpi speci?ation for details of the month alarm ?ld (offset 7eh) and century ?ld (offset 7fh). 4.5 enhanced ide controller registers 4.5.1 enhanced ide con guration registers (devb:1xxx) these registers are located in pci con?uration space on the primary pci interface, in the second device (device b), function 1. see section 4.1.2 on page 136 for a description of the register naming convention. bits description 7:0 rtcdata. real-time clock data. this is the data port for accesses to the real-time clock cmos ram that is indexed by rtc70. rtc70; cmos ram offset function range for binary mode range for bcd mode 7dh date alarm 01h-1fh 01h-31h 7eh month alarm 01h-0ch 01h-12h 7fh century eld 13h-63h 19h-99h chapter 4 registers 185 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information eide controller vendor and device id register devb:1x00 default: 7469 1022h. attribute: read-only. eide controller status and command register devb:1x04 default: 0200 0000h. attribute: see below. eide revision id, programming interface, sub class and base registers devb:1x08 default: 0101 8axxh see below. attribute: see below. bits description 31:16 eide controller device id. 15:0 vendor id. bits description 31:27 read-only. these bits is xed in the low state. 26:25 devsel timing. read-only. these bits are xed at status[10:9] = 01b. this speci es medium timing as de ned by the pci speci cation. 24:3 read-only. these bits are xed at their default values. 2 bmen. bus master enable. read-write. 1=enables ide bus master capability. 1 memory space enable. read-only. this bit is xed in the low state. 0 ioen. i/o space enable. read-write. 1=enables access to the i/o space for the ide controller. bits description 31:24 baseclass. read-only. these bits are xed at 01h indicating a mass storage device. 23:16 subclass. read-only. these bits are xed at 01h indicating an ide controller. 15 progif[7]. master ide capability. read-only. this bit is xed in the high state. 14:12 progif[6:4]. read-only. these bits are xed in the low state. 11 prog if[3]. secondary native/compatibility mode selectable. read-only. this is high to indicate that progif[2] is read-write. 186registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information eide controller bist, header and latency register devb:1x0c default: 0000 0000h. attribute: see below. eide controller primary command base address devb:1x10 default: 0000 01f1h. attribute: see below. 10 progif[2]. secondary native mode. read-write. 0=compatibility mode for secondary port; devb:1x18 and devb:1x1c are ignored and not visible; address decode is based on legacy addresses 170h-177h, 376h; devb:1x3c[7:0] read-only zeros; devb:1x3c[15:8] = 00h; irq15 may be used by the ide controller. 1=native mode; devb:1x18 and devb:1x1c are visible and used for address decode; devb:1x3c[7:0] read-write; devb:1x3c[15:8] = 01h; irq15 mapped to pirqa per section 3.4.2.1 on page 41 and used exclusively by the secondary ide port. 9 progif[1]. primary native/compatibility mode selectable. read-only. this is high to indicate that progif[0] is read-write. 8 progif[0]. primary native mode. read-write. 0=compatibility mode for primary port; devb:1x10 and devb:1x14 are ignored and not visible; address decode is based on legacy addresses 1f0h- 1f7h, 3f6h; devb:1x3c[7:0] read-only zeros; devb:1x3c[15:8] = 00h; irq14 may be used by the ide controller. 1=native mode; devb:1x10 and devb:1x14 are visible and used for address decode; devb:1x3c[7:0] read-write; devb:1x3c[15:8] = 01h; irq14 mapped to pirqa per section 3.4.2.1 on page 41 and used exclusively by the primary ide port. 7:0 revisionid. read-only. eide controller silicon revision. the value of this register is revision- dependent. bits description 31:24 bist. read-only. these bits xed at their default values. 23:16 header. read-only. these bits xed at their default values. 15:8 latency. read-write. this eld controls no hardware. 7:0 cache. read-only. these bits xed at their default values. bits description 31:3 base[31:3] port address. read-write. these bits specify an 8-byte i/o address space that maps to the ata-compliant command register set for the primary port (legacy i/o space 1f0h-1f7h). note: when devb:1x08[8] is low, the primary port is in compatibility mode and this register is ignored and not visible (reads as 0000_0000h). 2:0 read-only. 001b. bits description (continued) chapter 4 registers 187 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information eide controller primary control base address devb:1x14 default: 0000 03f5h. attribute: see below. eide controller secondary command base address devb:1x18 default: 0000 0171h. attribute: see below. eide controller secondary control base address devb:1x1c default: 0000 0375h. attribute: see below. eide controller bus master control registers base address devb:1x20 default: 0000 cc01h. attribute: see below. bits description 31:2 base[31:2] port address. read-write. these bits specify a 4-byte i/o address space that maps to the ata-compliant control register set for the primary port (legacy i/o space 3f4h-3f7h). note: when devb:1x08[8] is low, the primary port is in compatibility mode and this register is ignored and not visible (reads as 0000_0000h). note: only byte 2 (legacy i/o address 3f6h) of this space is used. 1:0 read-only. 01b. bits description 31:3 base[31:3] port address. read-write. these bits specify an 8-byte i/o address space that maps to the ata-compliant command register set for the secondary port (legacy i/o space 170h-177h). note: when devb:1x08[10] is low, the secondary port is in compatibility mode and this register is ignored and not visible (reads as 0000_0000h). 2:0 read-only. 001b. bits description 31:2 base[31:2] port address. read-write. these bits specify a 4-byte i/o address space that maps to the ata-compliant control register set for the secondary port (legacy i/o space 374h-377h). note: when devb:1x08[10] is low, the secondary port is in compatibility mode and this register is ignored and not visible (reads as 0000_0000h). note: only byte 2 (legacy i/o address 376h) of this space is used. 1:0 read-only. 01b. bits description 31:4 base[31:4] port address. read-write. this eld speci es the 16-byte i/o address space that maps to the eide controller register set that is compliant with the sff-8038i speci cation (bus master programming interface for ide ata controllers), ibmx. 3:0 read-only. 0001b. 188 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information eide subsystem id and subsystem vendor id register devb:1x2c default: 0000 0000h. attribute: read-only. eide controller interrupt line, interrupt pin, min. grant, max latency register devb:1x3c default: 0000 00ffh. attribute: see below. eide controller con guration register devb:1x40 default: 0000 04?0h. attribute: see below. bits description 31:16 ssid. subsystem id register. this eld is write accessible through devb:1x70. 15:0 ssvendorid. subsystem vendor id register. this eld is write accessible through devb:1x70. bits description 31:24 max latency. read-only. these bits are xed at their default values. 23:16 min gnt. read-only. these bits are xed at their default values. 15:8 interrupt pin. read-only. when either devb:1x08[8] or devb:1x08[10] is high, then eld reads as 01h. when they are both low, then it reads as 00h. 7:0 interrupt line. this register is either read-write or read-only based on the state of devb:1x08[10,8]. when either devb:1x08[8] or devb:1x08[10] is high, then this is a read-write register. when they are both low, then it is a read-only register, reading ffh. bits description 31:24 reserved. 23:20 rw. read-write. these bits control no hardware. 19:16 cable. read-write. these bits are intended to be programmed by bios to specify the cable type of each of the ide drives to the driver software. 1=high speed 80-pin cable is present. the bits specify the following drive: bit[16]: primary master. bit[18]: secondary master. bit[17]: primary slave. bit[19]: secondary slave. 15 rw. read-write. this bit controls no hardware. 14 pripwb. primary post write buffer. read-write. 1=the primary port posted-write buffer for pio modes is enabled. note: only 32-bit writes to the data register are allowed when this bit is set. 13 rw. read-write. this bit is read-write accessible through software; it controls no hardware. 12 secpwb. secondary post write buffer. read-write. 1=the secondary port posted-write buffer for pio modes is enabled. note: only 32-bit writes to the data register are allowed when this bit is set. 11 phyor. ata phy override. read-write. 1=ata phy slew rate controlled by devb:1x40[phyorsel]. 0=ata phy slew rate controlled by phy select circuitry observed in devb:1x40[physel]. 10 rw. read-write. this bit controls no hardware. 9:8 phyorsel. ata phy override select. read-write. these bits specify the override value of the phy speed select, as speci ed by devb:1x40[physel]. this eld is ignored when devb:1x40[phyor]=0. 7 reserved. this bit is xed to 0. chapter 4 registers 189 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information eide controller drive timing control register devb:1x48 this register speci?s timing for pio data transfers (1f0h and 170h or the native mode equivalents) and multi-word dma transfers. the value in each 4-bit ?ld, plus one, speci?s a time in 30 nanosecond pci clocks. notes: 1. for command and control transfers (1f1h-1f7h, 171h-177h, 3f6h and 376h) see devb:1x4c. 2. the default state, a8h, results in a recovery time of 270ns and an active pulse width of 330ns for a 30ns pci clock (total cycle time = 600ns) which corresponds to ata pio mode 0. 3. pio modes are controlled through devb:1x48 and devb:1x4c. to set the timing associated with the various modes, devb:1x4c should be left at its default value and the appropriate byte of devb:1x48 should be programmed as follows?ode 0=a8h; mode 1=65h; mode 2=42h; mode 3=22h; mode 4=20h. default: a8a8 a8a8h. attribute: read-write. 6:5 physel. phy speed select. read-only. these specify the selected phy speed selection as follows: 00b=bigger phy resistor (fast corner); 10b=medium phy resistor; x1b=smaller phy resistor (slow corner). the power-up default for these bits is device speci c. 4:2 reserved. these bits are xed to 0. 1 prien. primary channel enable. read-write. 1=the primary port of the eide controller is enabled. 0 secen. secondary channel enable. read-write. 1=the secondary port of the eide controller is enabled. bits description 31:28 pd0pw[3:0]. primary drive 0 data dior_l/diow_l active pulse width . 27:24 pd0rt[3:0]. primary drive 0 data dior_l/diow_l minimum recovery time . 23:20 pd1pw[3:0]. primary drive 1 data dior_l/diow_l active pulse width . 19:16 pd1rt[3:0]. primary drive 1 data dior_l/diow_l minimum recovery time . 15:12 sd0pw[3:0]. secondary drive 0 data dior_l/diow_l active pulse width . 11:8 sd0rt[3:0]. secondary drive 0 data dior_l/diow_l minimum recovery time . 7:4 sd1pw[3:0]. secondary drive 1 data dior_l/diow_l active pulse width . 3:0 sd1rt[3:0]. secondary drive 1 data dior_l/diow_l minimum recovery time . bits description (continued) 190 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information eide controller cycle time and address setup time register devb:1x4c for bits[7:0] the value in each 2-bit ?ld, plus one, speci?s the address setup time in 30 nanosecond pci clocks; this applies to all pio and multi-word dma cycles. for bits[31:16] the value in each 4- bit ?ld, plus one, speci?s the time in 30 nanosecond pci clocks; this applies to address ports 1f1h- 1f7h, 171h-177h, 3f6h, and 376h; for 1f0h and 170h, see devb:1x48. default: ffff 00ffh. attribute: read-write. bits description 31:28 pxpw[3:0]. primary command/control dior_l/diow_l active pulse width . 27:24 pxrt[3:0]. primary command/control dior_l/diow_l recovery time . 23:20 sxpw[3:0]. secondary command/control dior_l/diow_l active pulse width . 19:16 sxrt[3:0]. secondary command/control dior_l/diow_l recovery time . 15:8 reserved. 7:6 p0add[1:0]. primary drive 0 address setup time . 5:4 p1add[1:0]. primary drive 1 address setup time . 3:2 s0add[1:0]. secondary drive 0 address setup time . 1:0 s1add[1:0]. secondary drive 1 address setup time . chapter 4 registers 191 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information eide controller udma extended timing control register devb:1x50 the de?ition of each of the four 8-bit ?lds in this register are identical; they apply to different drives. default: 0303 0303h. attribute: read-write. here is the de?ition of each 8-bit ?ld: bits description 31:24 p0udma. primary drive 0 udma timing control. 23:16 p1udma. primary drive 1 udma timing control. 15:8 s0udma. secondary drive 0 udma timing control. 7:0 s1udma. secondary drive 1 udma timing control. bits description 31, 23, 15, 7 [p0, p1, s0, s1]enmode. [primary, secondary] drive [0, 1] ultra-dma mode enable method. 1=enable ultra-dma by setting bit 6 of this 8-bit register. 0=enable ultra-dma by detecting the set feature ata command. 30, 22, 14, 6 [p0, p1, s0, s1]udmaen. [primary, secondary] drive [0, 1] ultra-dma mode enable. 1=ultra-dma mode is enabled. 29:27, 21:19, 13:11, 5:3 reserved. 26:24, 18:16, 10:8, 2:0 [p0, p1, s0, s1]cyct[2:0]. [primary, secondary] drive [0,1] cycle time. cyct[2:0] ultra-dma mode cycle time 000b udma mode 2 (ata-33) 60 nanoseconds 001b udma mode 1 80 nanoseconds 010b udma mode 0 120 nanoseconds 011b slow udma mode 0 150 nanoseconds 100b udma mode 3 (ata-44) 45 nanoseconds 101b udma mode 4 (ata-66) 30 nanoseconds 110b udma mode 5 (ata-100) 20 nanoseconds 111b udma mode 6 (ata-133) 15 nanoseconds 192 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information eide power management register devb:1x54 this register controls the power state of the two ide ports. when an ide port is powered up, it is designed to be fully operational. when it is powered down, outputs daddr[s,p][2:0], dcs1[s,p]_l, dcs3[s,p]_l, ddack[s,p]_l, dio[r,w][s,p]_l and drst[s,p]_l are forced low; ddata[s,p][15:0], ddrq[s,p], and drdy[s,p] are ignored and in high-impedance mode. when transitioning into the power-down state, drst[s,p]_l assertion leads control over the rest of the signals by about 1 microsecond. when transitioning into the power-up state, drst[s,p]_l deassertion lags control over the rest of the signals by about 1 microsecond. note: writes to [s,p]pwrdn cause [s,p]pwrx to be set high until the power state transition is complete; while [s,p]pwrx is high, writes to [s,p]pwrdn are ignored. default: 00h. attribute: see below. read-write register devb:1x58 default: 0000h. attribute: read-write. bits description 7:6 reserved. 5 spwrx. power state transition for secondary ide port. read-only. 1=the secondary ide port is transitioning from either the power-down state to the power up state (if spwrdn = 0) or from the power-up state to the power-down state (if spwrdn = 1). 4 spwrdn. power down secondary ide port. writing a 1 to this eld causes the hardware to transition the secondary port from the powered-up state to the powered-down state. writing a 0 to this eld causes the hardware to transition the secondary port from the powered-down state to the powered-up state. when read, this bit re ects the last state written to it; however, it cannot be altered when spwrx is high. 3:2 reserved. 1 ppwrx. power state transition for primary ide port. read-only. 1=the primary ide port is transitioning from either the power-down state to the power up state (if ppwrdn = 0) or from the power-up state to the power-down state (if ppwrdn = 1). 0 ppwrdn. power down primary ide port. writing a 1 to this eld causes the hardware to transition the primary port from the powered-up state to the powered-down state. writing a 0 to this eld causes the hardware to transition the primary port from the powered-down state to the powered-up state. when read, this bit re ects the last state written to it; however, it cannot be altered when ppwrx is high. bits description 15:0 rw. read-write. these bits are read-write accessible through software; they control no hardware. chapter 4 registers 193 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information eide device and subsystem id read-write register devb:1x70 default: 0000 0000h. attribute: read-write. 4.5.2 eide bus master i/o registers these registers are located in i/o space. the base address register is devb:1x20. see section 4.1.2 on page 136 for a description of the register naming convention. these registers comply with sff-8038i for control of dma transfers between drives and system memory. primary bus master ide command register ibm0 default: 00h. attribute: see below. primary bus master ide status register ibm2 default: 00h. attribute: see below. bits description 31:16 ssid. subsystem id register. the value placed in this register is visible in devb:1x2c[31:16]. 15:0 ssvendorid. subsystem vendor id register. the value placed in this register is visible in devb:1x2c[15:0]. bits description 7:4 reserved. these bits are xed to 0000b. 3 rwctl. read or write control. read-write. 1=read cycles speci ed (read from the drive; write to system memory). 0=write cycles speci ed. 2:1 reserved. these bits are xed to 00b. 0 stsp. start/stop bus master. write-only; reads always return 0. bits description 7 simplex only. read-only. this bit is xed to 0b. both bus masters are able to operate independently. 6 dma1c. drive 1 dma capable. read-write 5 dma0c. drive 0 dma capable. read-write. 4:3 reserved. these bits are xed to 00b. 2 irq. interrupt. read; set by hardware; write 1 to clear. this bit is set by the rising edge of the ide interrupt line. 1 err. error. read; write 1 to clear. 0 actv. bus master ide active. read-only. 194 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information primary bus master ide prd table address register ibm4 default: 0000 0000h. attribute: see below. secondary bus master ide command register ibm8 default: 00h. attribute: see below. secondary bus master ide status register ibma default: 00h. attribute: see below. secondary bus master ide prd table address register ibmc default: 0000 0000h. attribute: see below. bits description 31:2 pprdadd[31:2]. primary physical region descriptor table base address. read-write. 1:0 pprdadd[1:0]. read-only. these bits are xed in the low state. bits description 7:4 reserved. these bits are xed to 0000b. 3 rwctl. read or write control. read-write. 1=read cycles speci ed (read from the drive; write to system memory). 0=write cycles speci ed. 2:1 reserved. these bits are xed to 00b. 0 stsp. start/stop bus master. write-only; reads always return 0. bits description 7 simplex only. read-only. this bit is xed to 0b. both bus masters are able to operate independently. 6 dma1c. drive 1 dma capable. read-write 5 dma0c. drive 0 dma capable. read-write. 4:3 reserved. these bits are xed to 00b. 2 irq. interrupt. read; set by hardware; write 1 to clear. this bit is set by the rising edge of the ide interrupt line. 1 err. error. read; write 1 to clear. 0 actv. bus master ide active. read-only. bits description 31:2 sprdadd[31:2]. secondary physical region descriptor table base address. read-write. 1:0 sprdadd[1:0]. read-only. these bits are xed in the low state. chapter 4 registers 195 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 4.6 system management bus 2.0 controller registers 4.6.1 system management bus con guration registers (devb:2xxx) smbus controller vendor and device id devb:2x00 default: 746a_1022h attribute: read-only. smbus controller command and status devb:2x04 default: 0200_0000h attribute: see below. smbus controller revision id and class code devb:2x08 this register is aliased to devb:2x40 for write access. default: 0c05_00xxh see below. attribute: read-only. bits description 31:16 smbid. provides the smbus controller device identi cation. 15:0 amdid. provides amd s pci vendor identi cation. bits description 31:16 stat. read-only. 15:0 cmd. cmd[15:1]: read-only. cmd[0]: i/o space enable, ioen. read-write. 1b = access to i/o space for this device is enabled. 0b = access to i/o space for this device is disabled. bits description 31:24 baseclass. these bits are xed at 0ch indicating a serial bus controller. 23:16 subclass. these bits are xed at 05h indicating a smbus controller. 15:8 progif. 7:0 revid. smbus controller silicon revision . the value of this register is revision-dependent. 196registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information smbus controller bist, header and latency devb:2x0c default: 0000_0000h attribute: see below. smbus controller command interface base address devb:2x10 default: 0000_0001h attribute: see below. smbus controller subsystem and subsystem vendor id devb:2x2c this register is aliased to devb:2x44 for write access. default: 0000_0000h attribute: read-only. smbus controller interrupt line and interrupt pin devb:2x3c default: 0000_0400h attribute: see below. bits description 31:24 bist. read-only. 23:16 header. read-only. 15:8 latency. read-write. the latency timer de nes the minimum amount of time, in pci clock cycles, that the bus master can retain ownership of the bus. 7:0 read-only. bits description 31:5 ciba. command interface base address . read-write. these bits are used in the i/o space decode of the sc interface registers. there is a maximum block size of 32 bytes for this base address. 4:1 read-only. 0 rte. resource type indicator. this bit is xed to 1, indicating i/o address space. bits description 31:16 subsysid. subsystem id . 15:0 subvenid. subsystem vendor id . bits description 31:11 reserved. 10:8 intpin. read-only. indicates which pci interrupt pin is used for the smbus controller interrupt. hardwired to 100b to select pirqd. 7:0 intline. read-write. this data is not used by hardware. it is used to communicate across software the interrupt line that the interrupt pin is connected to. chapter 4 registers 197 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information smbus controller revision id and class code alias devb:2x40 default: 0c05_0001h attribute: see below. smbus controller subsystem and subsystem vendor id alias devb:2x44 default: 0000_0000h attribute: read-write smbus controller miscellaneous control devb:2x48 note: this register resides on the vdd_corex power plane and is cleared to its default value only when coming out of mechanical off power state (moff). default: 0000_0006h attribute: see below. 4.6.2 smbus controller interface registers the command interface registers are located in i/o space and provide an acpi 2.0 chapter 13 compliant interface for communication with the smbus controller. refer to the acpi 2.0 chapter 13 for a detailed description of the interface operation. the base address register for these registers is devb:2x10. see section 4.1.2 on page 136 for a description of the register naming convention. bits description 31:24 baseclass. read-write. these bits default to 0ch indicating a serial bus controller. 23:16 subclass. read-write. these bits default to 05h indicating a smbus controller. 15:8 progif. read-write. 7:0 revid. smbus controller silicon revision . read-only. 01h = revision a0. bits description 31:16 subsysid. subsystem id . 15:0 subvenid. subsystem vendor id . bits description 31:3 reserved. 2 set_scists_en. when set to 1b setting of sc04[sci_evt] or sc04[obf] or clearing of sc04[ibf] sets pm20[smbc_sts]. 1 set_intsts_en. when set to 1b setting of sc04[sci_evt] or sc04[obf] or clearing of sc04[ibf] sets sc08[int_sts]. 0 su. smbus clock speed-up . read-write. when set to 1b the nominal smbus clock rate is increased by 16x. 198 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information data register sc00 default: 0000h attribute: read-write status register sc04 this register is aliased to the same address as command (sc04) but provides only read access. default: 00h attribute: read-only. bits description 7:0 data. data port . this register acts as a port for transferring data between the host and the smbus controller. writes to this port by the host are stored in the internal input data register. reads from this register return data from the internal output data register. bits description 7:6 reserved. 5 sci_evt. sci event pending . 1: sci event is pending (requesting sci query). 0: no sci events are pending. this bit is set by hardware when one of the events enabled by sc08[smbalert_en] or indicated by smb08[done, alrm, status] occurs. when enabled by devb:2x48[set_scists_en] setting this bit also sets pm20[smbc_sts]. when enabled by devb:2x48[set_intsts_en] setting this bit also sets sc08[int_sts]. this bit is cleared by hardware when all noti cation headers were cleared by query commands from the host. 4 burst. burst mode . 1: controller is in burst mode for polled command processing. 0: controller is in normal mode for interrupt-driven command processing. this bit indicates that the controller has received the burst enable command from the host, has halted normal processing, and is waiting for a series of commands to be sent from the host. this bit is set by the controller upon receiving the burst acknowledge command (0x90) and cleared upon receiving the burst disable command (0x83). chapter 4 registers 199 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information command register sc04 this register is aliased to the same address as status (sc04) but provides only write access. default: 00h attribute: write-only. interrupt control register sc08 default: 00h attribute: read-write. 3 cmd. command byte . 1: byte in the internal input data register is a command byte. 0: byte in the internal input data register is a data byte. this bit is set by hardware upon write access to sc04 by the host. this bit is cleared by hardware upon write access to sc00 by the host. 2 reserved. 1 ibf. input buffer full . 1: input buffer is full. 0: input buffer is empty. this bit is set by hardware upon write access to either sc00 or sc04 by the host. this bit is cleared by hardware when the controller reads its internal input data register. 0 obf. output buffer full . 1: output buffer is full. 0: output buffer is empty. this bit is set by hardware when the controller places data into its internal output data register. this bit is cleared by hardware upon read access to sc00 by the host. bits description 7:0 cmd. command port. data port. this register acts as a port for transferring commands from the host to the smbus controller. writes to this port by the host are stored in the internal input data register. bits description 7:4 reserved. bits description 200 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 4.6.3 host controller interface registers the host controller interface registers are located in the internal address space of the smbus controller and provide an acpi 2.0 chapter 13.9 compliant interface for communication with the host controller. refer to the acpi 2.0 chapter 13.9 for a detailed description of the interface operation. access for host operations is provided through the smbus controller interface register sc00 and sc04. these registers reside on the vdd_corex power plane and are only cleared to their default values when coming out of the mechanical off power state (moff). protocol register smb00 this register determines the type of smbus transaction generated on the smbus. writing to this register initiates the transaction on the smbus. default: 00h attribute: read-write. 3 smbalert_en. smbalert enable . 1b enables an internal noti cation header of 80h to be set and sc04[sci_evt] to be set when an smbalert event occurs. note: this bit resides on the vdd_corex power plane and is cleared to its default value only when coming out of the mechanical off power state (moff). 2 reserved. 1 int_en. interrupt enable . 1: pci interrupt is driven when int_sts is set. 0: pci interrupt disabled. 0 int_sts. interrupt status . this bit is set by hardware upon setting of sc04[sci_evt] or sc04[obf] or clearing of sc04[ibf] when enabled by devb:2x48[set_intsts_en]. this bit is cleared by writing 1b to this position. bits description 7 pec. packet error checking enable . 1: pec format used for the speci ed protocol. 0: standard (non-pec) format used for the speci ed protocol. 6:0 prtcl. smbus protocol . this register determines the type of smbus transaction generated on the smbus. in addition to the commands described in the acpi 2.0 speci cation the host controller also supports the following commands: 0x4a block write i2c 0x4b block read i2c chapter 4 registers 201 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information status register smb01 this register is cleared by hardware (except for the alrm bit) whenever a new command is issued using a write access to smb00. any bit of this register being set causes an internal noti?ation header of 20h to be set and sc04[sci_evt] to be set. default: 00h attribute: see below. address register smb02 default: 00h attribute: read-write. bits description 7 done. command completion . read-only. 1b indicates the last command has completed without error. 6 alrm. read/clear by write. 1b indicates an smbus alarm message has been received. this bit is cleared by writing 00h to smb01. 5 reserved. 4:0 status. read-only. smbus status. indicates smbus communication status as listed in the table below. table 57. smbus status status code name description 00h smbus ok indicates the transaction has been successfully completed 10h smbus device address not acknowledged indicates the transaction failed because the slave device address was not acknowledged. 11h smbus device error detected indicates the transaction failed because the slave device not acknowledged another byte 18h smbus timeout indicates the transaction failed because the smbus host detected a timeout on the bus 19h smbus host unsupported protocol indicates the transaction failed because the smbus host does not support the requested protocol 1ah smbus busy or arbitration lost indicates the transaction failed because the smbus host reports that: - arbitration lost or - smbus was busy for a time longer than 40,96 ms 1fh smbus pec (crc-8) error indicates that a packet error checking (pec) error occurred during the last transaction. bits description 7:1 addr. smbus address . this register contains the 7 bit address for smbus transactions. 0 reserved. 202 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information command register smb03 default: 00h attribute: read-write. data registers smb04-smb23 this bank of registers contains the bytes to be sent or received in any smbus transaction. the registers are de?ed on a per-protocol basis and, as such, provide ef?ient use of register space. default: 00h attribute: read-write. block count register smb24 default: 00h attribute: read-write. alarm address register smb25 default: 00h attribute: read-write. bits description 7:0 cmd. smbus command . this register contains the command byte that is sent to the smbus device and is used for the following protocols send byte, write byte, write word, read byte, read word, process call, block read, block write, block read i2c and block write i2c. it is not used for the quick commands or the receive byte protocol, and as such, its value is a don t care for those commands bits description 7:0 data. smbus data . bits description 7:5 reserved. 4:0 bcnt. block count . this register contains the number of bytes of data present in the smb[23:04] preceding any write block and following any read block transaction. for the read block i2c transaction the bcnt register contains the number of bytes to be received. the data size is de ned on a per protocol basis. the following encoding is used: 00001: 1 byte 00010: 2 bytes ... 00000: 32 bytes bits description 7:1 addr. alarm address . this register contains the address of an alarm message indicating the slave address of the device on the smbus that initiated the alarm message. 0 reserved. chapter 4 registers 203 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information alarm data register smb26-smb27 default: 00h attribute: read-write. 4.7 system management registers 4.7.1 system management con guration registers (devb:3xxx) these registers are located in pci con?uration space on the primary pci interface, in the second device (device b), function 3. see section 4.1.2 on page 136 for a description of the register naming convention. system management vendor and device id register devb:3x00 default: 746b 1022h. attribute: read-only. system management status and command register devb:3x04 default: 0280 0000h. attribute: read-only. system management revision and class code register devb:3x08 default: 0000 00xxh see below. attribute: read-only. bits description 7:0 data. alarm data . these registers contain the two data bytes of an alarm message indicating the speci c reason for the alarm message. once an alarm message has been received, the host controller will not receive additional alarm messages until the smb01[alrm] is cleared. bits description 31:16 system management device id. 15:0 vendor id. bits description 31:0 these bits are xed at their default values. bits description 31:8 classcode. this eld is write accessible through devb:3x60. 7:0 revision. system management silicon revision . the value of this register is revision-dependent. 204 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information system management bist-header-latency-cache register devb:3x0c default: 0000 1600h. attribute: see below. system management subsystem id and subsystem vendor id register devb:3x2c default: 0000 0000h. attribute: read-only. general con guration 1 register devb:3x40 default: 00h. attribute: read-write. bits description 31:24 bist. read-only. these bits xed at their default values. 23:16 header. read-only. these bits xed at their default values. 15:8 latency. read-write. this eld controls no hardware. 7:0 cache. read-only. these bits xed at their default values. bits description 31:16 ssid. subsystem id register. this eld is write accessible through devb:3x7c. 15:0 ssvendorid. subsystem vendor id register. this eld is write accessible through devb:3x7c. bits description 7 rngen. random number generated enable. read; write to 1 only. 1=the rng (accessible through pmf0 and pmf4) is enabled to generate random numbers. 0=the rng is disabled. this bit can only be written to a 1; writing a 0 has no effect. 6 stoptmr. stop acpi timer from counting. 1=acpi timer, pm08, stops counting (frozen in its current state). 0=acpi timer enabled to count. 5:4 thminen. throttling minimum enable time. these bits specify the minimum time in which stpclk_l is held in the deasserted state during throttling (normal or thermal), regardless of the state of the throttling duty cycle registers, devb:3x4d and pm10. these bits do not affect the throttling cycle period; if the throttling duty cycle speci es a stpclk_l deassertion time that is less than speci ed by this register, then the stpclk_l assertion time is reduced. this has no effect on throttling in which the period is 244 microseconds. thminen time 00b none. 01b 10 microseconds. 10b 20 microseconds. 11b reserved. chapter 4 registers 205 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information general con guration 2 register devb:3x41 default: 41h. attribute: see below. sci interrupt con guration register devb:3x42 default: 00h. attribute: read-write. 3 ntper. normal throttling period. 1=normal throttling cycle period speci ed to be 244 microseconds (from an asserting edge of stpclk_l to the next asserting edge). minimum ldtstop_l assertion during throttling if devb:3x70[ntls]=1 is 16us. 0=normal throttling period speci ed to be 30 microseconds. minimum ldtstop_l assertion during throttling if devb:3x70[ntls]=1 is 2us. 2 ttper. thermal throttling period. 1=thermal throttling cycle period speci ed to be 244 microseconds (from an asserting edge of stpclk_l to the next asserting edge). minimum ldtstop_l assertion during throttling if devb:3x70[ttls]=1 is 16us. if 0=thermal throttling period speci ed to be 30 microseconds. minimum ldtstop_l assertion during throttling if devb:3x70[ttls]=1 is 2us. 1 reserved. 0 th2sd. throttling 2 second delay. 1=there is a 2.0 to 2.5 second delay after therm_l is asserted before thermal throttling is initiated, as speci ed by devb:3x4d. 0=initiate throttling immediately after therm_l is asserted. bits description 7 pmioen. system management i/o space enable. read-write. 1=pmxx, the i/o space speci ed by devb:3x58, is enabled. 6 tmrrst. acpi timer reset. read-write. 1=the acpi timer, pm08, is asynchronously cleared at all times. 0=the timer is allowed to count. 5 pcf9en. port cf9 enable. read-write. 1=access to portcf9 is enabled. 4 pbin. power button in. read-only. this bit re ect the current state of the pwrbtn_l pin (before the debounce circuit). 0=pwrbtn_l is currently asserted. 3 tmr32. timer size selection. read-write. 0=the acpi timer, pm08, is 24 bits. 1=the acpi timer is 32 bits. 2:1 reserved. 0 must be high. read-write. this bit is required to be high at all times; setting it low results in unde ned behavior. bits description 7:4 reserved. 3:0 scisel. sci interrupt selection. this eld speci es the irq number routed to the interrupt controllers used for acpi-de ned sci interrupts. a value of 0h disables sci interrupts. values of 2h, 8h, and dh are reserved. all other values are valid. see section 3.4.2.1 on page 41 for details about sci interrupt routing. bits description 206registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information previous power state register devb:3x43 default: see ?ld speci?ations below. attribute: see below. bits description 7 vdda_sts. al reset status. read; set by hardware; write 1 to clear. 1=al became invalid. this bit resides on the vdd_coreal plane. 6 g3tos5. mechanical off (g3) to soft off (s5). read; write. 0=when power is applied to the aux planes, the system automatically transitions into the fon state. 1=when power is a applied to the aux planes, the system enters the soff state. this bit resides on the vdd_coreal plane. when vdd_coreal powers up, this bit defaults to 0; when there is a reset_l generated by a write to portcf9[rstcmd, sysrst] == 11b, then this bit is cleared. 5:3 pwrfl_sts. power failure status. read; updated by hardware; write 1 to lsb to reset to 4h. if power fails (system enters moff or pwrok goes from 1 to 0 while pwron_l is asserted), then this register captures and retains the state the system was in when the failure occurred. this eld resides on the vdd_coreal plane. this eld defaults to 4h when vdd_coreal powers up. writing a one to devb:3x43[3] sets this eld to 4h; writing a zero to dev0:3x43[3] or writing any value to any other bits in this eld has no effect. the possible states are: pwrfl_sts power state pwrfl_sts power state 0h fon full on 4h no ac power failure 1h pos power on suspend 5h str suspend to ram 2h c2 6h std suspend to disk 3h c3 7h soff soft off this bit needs to be reset in order to allow the next power failure status to be captured. 2:0 ppstate. previous power state. read-only. this eld holds the most previous power state from which the system came into the fon state. this eld resides on the vdd_corex plane. here are the possible states: ppstate power state ppstate power state 0h reserved 4h moff mechanical off 1h pos power on suspend 5h str suspend to ram 2h c2 6h std suspend to disk 3h c3 7h soff soft off chapter 4 registers 207 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information pnp irq select register devb:3x44 bits[11:0] assign pnpirq[2:0] pins to irqs that are routed to interrupt controllers; see section 3.4.2.1 on page 41 for more details. default: 0000h. attribute: read-write. pins latched on the trailing edge of reset register devb:3x48 the default for all of these bits is speci?d by pull up or pull down resistors on pins during the trailing edge of the speci?d reset (pwrok). to latch a low on these pins, a 10k to 100k ohm resistor to ground is placed on the signal. to latch a high on these pins, a 10k to 100k ohm resistor to the pin s power plane is placed on the signal. default: each of these bits is latched on the trailing edge of reset. attribute: see below. bits description 15 tco_int_en. tco interrupt enable. 1=enable tco irq selected by devb:3x44[tco_int_sel] (if pm22[tcosci_en] = 0). 14:12 tco_int_sel. tco interrupt select. speci es the irq line asserted by either pm46[intrdr_sts] (if pm4a[intrdr_sel] selects irq) or pm44[tco_int_sts]. note: if pm22[tcosci_en] is set, then this eld is ignored. note: if one of irq[11:9] is selected, then the interrupt controller must be programmed as level sensitive for this irq. tco_int_sel interrupt tco_int_sel interrupt 0h irq9 4h apic irq20 1h irq10 5h apic irq21 2h irq11 6h apic irq22 3h reserved 7h apic irq23 11:8 irq2sel. pnpirq2 interrupt select. this selects the irq number for pnpirq2. irq0, irq2, irq8, and irq13 are reserved. if pmd5 does not select the pnpirq2 function then this eld has no effect. see section 3.4.2.1 on page 41 for more details. 7:4 irq1sel. pnpirq1 interrupt select. this selects the irq number for pnpirq1. irq0, irq2, irq8, and irq13 are reserved. if pmd4 does not select the pnpirq1 function then this eld has no effect. see section 3.4.2.1 on page 41 for more details. 3:0 irq0sel. pnpirq0 interrupt select. this selects the irq number for pnpirq0. irq0, irq2, irq8, and irq13 are reserved. if pmd3 does not select the pnpirq0 function then this eld has no effect. see section 3.4.2.1 on page 41 for more details. bits description 15 tbd15. read-only. the state of this bit is latched off of ad[15] at the trailing edge of pwrok reset. this bit controls no internal hardware. 14 tbd14. read-only. the state of this bit is latched off of ad[14] at the trailing edge of pwrok reset. this bit controls no internal hardware. 13 tbd13. read-only. the state of this bit is latched off of ad[13] at the trailing edge of pwrok reset. this bit controls no internal hardware. 12 spkrl. spkr latch. read-write. the state of this bit is latched off of spkr at the trailing edge of pwrok reset. this controls no internal logic. 208 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 11 cmpovr. hypertransport technology automatic compensation override. read-write. 1=the compensation values speci ed by deva:0xe0[rx_orc, txn_orc, and txp_orc] are used by the hypertransport phy. 0=the automatic phy compensation circuit values are used by the hypertransport phy. the state of this bit is latched off of ad[11] at the trailing edge of pwrok reset. 10 no_reboot. do not reboot the system when a double tco timer time out occurs. read-write. 0=reboot system as speci ed by portcf9[fullrst] when pm46[2ndto_sts] is set. 1=do not reboot the system. the state of this bit is latched off of ad[10] at the trailing edge of pwrok reset. 9 low strap required. read-write. the default state of this bit is latched off of ad[9] at the trailing edge of pwrok reset. this bit is required to be low at all times; if it is high then unde ned behavior results. 8 low strap required. read-only. the default state of this bit is latched off of ad[8] at the trailing edge of pwrok reset. this bit is required to be low at all times; if it is high then unde ned behavior results. 7 low strap required. read-write. the default state of this bit is latched off of ad[7] at the trailing edge of pwrok reset. this bit is required to be low at all times; if it is high then unde ned behavior results. 6 tbd6. read-only. the state of this bit is latched off of ad[6] at the trailing edge of pwrok reset. this bit controls no internal hardware. 5 high strap required. read-write. the default state of this bit is latched off of ad[5] at the trailing edge of pwrok reset. this bit is required to be high at all times; if it is low then unde ned behavior results. 4 low strap required. read-write. the default state of this bit is latched off of ad[4] at the trailing edge of pwrok reset. this bit is required to be low at all times; if it is high then unde ned behavior results. 3 tbd3. read-only. the state of this bit is latched off of ad[3] at the trailing edge of pwrok reset. this bit controls no internal hardware. 2 low strap required. read-only. the default state of this bit is latched off of ad[2] at the trailing edge of pwrok reset. this bit is required to be low at all times; if it is high then unde ned behavior results. 1 low strap required. read-only. the default state of this bit is latched off of ad[1] at the trailing edge of pwrok reset. this bit is required to be low at all times; if it is high then unde ned behavior results. 0 pcibios. read-write. this is speci es routing of accesses to bios address space (speci ed by devb:0x43). 1b = bios address space is located on the pci bus. 0b = bios address space is located on the lpc bus. the state of this bit is latched off of ad[0] at the trailing edge of reset. bits description (continued) chapter 4 registers 209 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information serial irq control register devb:3x4a default: 10h. attribute: read-write. prdy timer control register devb:3x4c each of these bits controls the ability of the prdy input signal to disable internal counters. when prdy becomes active then the counters that correspond to the active bits in this register stop counting until prdy becomes inactive. default: 00h. attribute: read-write. thermal throttling register devb:3x4d default: 00h. attribute: read-write. bits description 7 reserved. 6 contmd. continuous mode selected versus quiet mode. 1=the serial irq logic is in continuous mode. 0=the serial irq logic is in quiet mode. in continuous mode, the start frame is initiated by the ic immediately following each stop frame. in quiet mode, start frames are initiated by external slave devices. 5:2 frames. number if irq frames for a serial irq cycle. this speci es the number of 3-clock irq frames that the ic generates, during a serial irq cycle before, issuing the stop frame. per the serial irq speci cation, the number of frames is 17 plus the value of this eld. 1:0 startclks. number of clocks in start pulse. this speci es the size of the start pulse over serirq during the start frame of a serial irq cycle (including the slave cycle if in quiet mode) in pclk cycles. 00b = 4 cycles. 01b = 6 cycles; 10b = 8 cycles and 11b = reserved. bits description 7:3 reserved. 2 smt_dis. system management timer disable. 1=the all the system management timers speci ed by the pmxx space are disabled from counting while prdy is active. these include the acpi timer at pm08, re-trigger timers at pm[8c:50], the system inactivity timer at pm98, and the general purpose timer at pm94. 1 rtc_dis. real-time clock disable. 1=the real-time clock s counters that are clocked off of the 32 khz clock are disabled from counting while prdy is active. 0 pit_dis. programmable interval timer disable. 1=the clock to the three timers of the internal pit are disabled when prdy is active. bits description 7:6 reserved. 210 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information read-write register devb:3x4e default: 00h. attribute: read-write. c2/c3 state control register devb:3x4f default: 00h. attribute: read-write. 5 tthlock. thermal throttling lock. write 1 only. 1=writes to tth_en and tth_ratio are disabled. once set, this bit cannot be cleared by software. it is only cleared by a reset_l. tth_en and tth_ratio may change during the write command that sets tthlock high. 4 tth_en. thermal throttling enable. 1=thermal throttling is enabled when therm_l is asserted. 0=thermal throttling cannot be enabled. 3:1 tth_ratio. thermal throttling duty cycle. these specify the duty cycle of stpclk_l when the system is in thermal throttling mode (initiated by the therm_l pin when enabled by tth_en). the eld is decoded as follows: tth_ratio description tth_ratio description 0h reserved 4h 50.0% in stop grant state 1h 87.5% in stop grant state 5h 37.5% in stop grant state 2h 75.0% in stop grant state 6h 25.0% in stop grant state 3h 62.5% in stop grant state 7h 12.5% in stop grant state 0 reserved. bits description 7:4 reserved. 3:0 rw. these bits control no hardware. bits description 7:6 reserved. 5 astp_c3en. enable agpstop_l assertion during c3. 1=enables the assertion of agpstop_l during c3. 4 reserved. 3 cslp_c3en. enable cpusleep_l assertion during c3. 1=enables the control of the processor sleep_l pin during the c3 state transition. 0=cpusleep_l is always high. this bit has no effect if the pmc6 does not select the cpusleep_l function. 2 reserved. 1 c3en. enable c3 command. 1=enables the ic to place the processor into the stop grant state by asserting stpclk_l when pm15 is read. note, this bit must be high for cslp_c3en bits to function during the transition to c3. 0 c2en. enable c2 command. 1=enables the ic to place the processor into the stop grant state by asserting stpclk_l when pm14 is read. 0=disable. chapter 4 registers 211 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information power on suspend control register devb:3x50 this register speci?s the action taken by the ic when the sleep command is sent to pm04 with slp_typ indicating power on suspend. note: if posen is low, then the rest of the bits in this register are ignored. default: 8000h. attribute: read-write. bits description 15 pitrsm_l. enable the pit to generate unmasked interrupts during pos. 1=pit does not generate an interrupt to the pic or ioapic while in pos (starting from the time that the command to enter pos is sent to pm04); this may be used to prevent timer-tick interrupts from resuming the system while in pos. 0=pit generates an interrupt to the pic or ioapic while in pos. 14 msrsm_l. enable the mouse interrupt to generate unmasked interrupts during pos. 1=disable interrupt from both the irq12 pin and irq 12 of the serial irq logic to the pic or ioapic while in pos (starting from the time that the command to enter pos is sent to pm04); this may be used to prevent mouse interrupts from resuming the system while in pos. 0=enable interrupt to the pic or ioapic while in pos. 13:9 reserved. 8 susp. enable suspend_l assertion during pos. 1=enables the control of the suspend_l pin during pos. 7 reserved. 6 cslp. enable cpusleep_l assertion during pos. 1=enables assertion of the cpusleep_l pin during pos. 0=disable. this bit has no effect if the pmc6 does not select the cpusleep_l function. 5 dcstp. enable dcstop_l assertion during pos. 1=enables assertion of the dcstop_l pin during pos. this bit has no effect if the pmc8 does not select the dcstop_l function. 4 astp. enable agpstop_l assertion during pos. 1=enables assertion of the agpstop_l pin during pos. this bit has no effect if the pmc1 does not select the agpstop_l function. 3 pstp. enable pcistop_l assertion during pos. 1=enables the control of the pcistop_l pin during pos. 2 cstp. enable cpustop_l assertion during pos. 1=enables control of the cpustop_l pin during pos. this bit has no effect if the pmc7 does not select the cpustop_l function. 1 rw. read-write. this bit is read-write accessible through software; it controls no hardware. 0 posen. enable stop grant during pos. 1=enables the ic to place the processor into the stop grant state by asserting stpclk_l when a pos commands is sent to pm04. this bit required to be set high for any other bits in this register to be enabled. 212 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information misc acpi timing register devb:3x52 default: 0000h. attribute: read-write. pll lock timer register devb:3x54 default: 0fh. attribute: read-write. pci irq routing register devb:3x56 default: 0000h. attribute: read-write. bits description 15:2 reserved. 1:0 c3_astp_dt. c3 agpstop_l deassertion delay time. speci es the delay between ldtstop_l deassertion and agpstop_l deassertion when exiting c3 as follows: 00 = 1us (minimum, allowable positive tolerance 10%) 01 = 32us (+/ 10%) 10 = 64us (+/ 10%) 11 = 128us (+/ 10%) bits description 7:4 pllcnt1. pll lock timer count 1. speci es the pll recovery time as follows: pll synchronization time = (pllcnt + 1) * 61.035 microseconds. 3:0 pllcnt. pll lock timer count. speci es the pll recovery time as follows: pll synchronization time = (pllcnt + 1) * 61.035 microseconds. see section 3.7.1.6.5 on page 63 for details about this timer. bits description 15:12 pirqd_l select. see bits[3:0]. 11:8 pirqc_l select. see bits[3:0]. 7:4 pirqb_l select. see bits[3:0]. 3:0 pirqa_l select. these map the pci irq pins to the internal interrupt controller (pic and apic). these are decoded as follows: pirq[a,b,c,d]_l selectsselected irq pirq[a,b,c,d]_l selectsselected irq 0h none 8hreserved 1h irq1 9hirq9 2h reserved ahirq10 3h irq3 bhirq11 4h irq4 chirq12 5h irq5 dhreserved 6h irq6 ehirq14 7h irq7 fhirq15 chapter 4 registers 213 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information pmxx system management i/o space pointer devb:3x58 default: 0000 dd01h. attribute: see below. system management class code write register devb:3x60 default: 0000 0000h. attribute: read-write. clock control register devb:3x64 this register resides on the vdd_corex power plane. default: 0000 0013h. attribute: read-write. bits description 31:16 reserved. 15:8 pmbase. read-write. speci es pci address bits[15:8] of the 256-byte block of i/o-mapped registers used for system management (address space pmxx). access to this address space is enabled by devb:3x41[pmioen]. 7:0 pmblsb. read-only. these xed bits read 01h. bits description 31:8 ccwrite. the value placed in this register is visible in devb:3x08. 7:0 reserved. bits description 7:6 reserved. 5 smb1_db. smbusc0 debounce. (revision c0 and later) . 1=enable the smbus 1.0 controller clock input debounce logic. when the smbusc0 signal is asserted high or low for less than 60ns, the debounce logic does not propogate a change of the signal value to the internal logic. the signal must be asserted for at least 80ns to be safely detected by the internal logic. smbc_en must be set for the debounce logic to function. 0=disable smbusc0 debounce logic. note: the functionality of the smbus 1.0 controller apart from the debounce logic is not affected by the value of smbc_en. 214 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information system management action field register devb:3x70 this register includes eight 4-bit groups, one for each of several system management events. the registers specify whether ldtstop_l is asserted for the system management event and the system management action ?ld (smaf) associated with the event (ldtstop_l cannot be asserted for c2, so this bit is reserved; ldtstop_l is always asserted for vid/fid, so this bit is reserved). for each ldtstop_l assertion bit: 1=ldtstop_l is asserted after the stop grant cycle associated with the stpclk_l assertion; ldtstop_l is deasserted prior to each stpclk deassertion message. 0=ldtstop_l is not asserted for the system management event. for each smaf ?ld: the bits are applied to bits[3:1] of the hypertransport technology system management stpclk assertion and deassertion messages sent to the host for the system management event. default: 0000 0000h. attribute: read-write. 4 smbc_en. smbus controller clock enable. 1=enable the clock to the smbus controller. 0=disable the clock to the smbus controller. whenever the smbus controller clock is disabled, then reset is asserted to that device. 3:2 reserved. 1 l7_s3en. lan ethernet controller clock enable. see bit [0]. 0 l7_en. lan ethernet controller clock enable. bits [1] and [0] control the enable to the clock that is used by the lan ethernet controller as follows: l7_en l7_s3en fon, pos str, std, soff comment 0 0 no clock no clock power savings mode. 0 1 no clock no clock power savings mode. 1 0 clock enabled no clock lan ethernet controller not enabled for wake on lan. the corresponding mii interface is not driven during str, std, and soff. 1 1 clock enabled clock enabled lan ethernet controller enabled for wake on lan. whenever the lan ethernet controller is in a no-clock state, then reset is asserted to that device. bits description 31 ttls. thermal throttling ldtstop_l assertion. 30:28 ttsmaf. thermal throttling system management action eld. 27 ntls. normal throttling ldtstop_l assertion. 26:24 ntsmaf. normal throttling system management action eld. 23 reserved. 22:20 strsmaf. suspend to ram system management action eld. this applies to the stpclk cycle associated with str after pm04[slp_typ] is written with the str value. bits description (continued) chapter 4 registers 215 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information vid/fid ldtstop_l time register devb:3x74 default: 00h. attribute: read-write. 19 posls. power on suspend ldtstop_l assertion. this applies to the stop grant cycle associated with pos after pm04[slp_typ] is written with the pos value. 18:16 possmaf. power on suspend system management action eld. this applies to the stpclk cycle associated with pos after pm04[slp_typ] is written with the pos value. 15 reserved. 14:12 vfsmaf. vid/fid system management action eld. this applies to the stpclk cycle associated with the hypertransport technology system management vid/fid change request message. 11 c3ls. c3 ldtstop_l assertion. this applies to the stop grant cycle associated with c3 after pm15 is accessed. 10:8 c3smaf. c3 system management action eld. this applies to the stpclk cycle associated with c3 after pm15 is accessed. 7 reserved. 6:4 c2smaf. c2 system management action eld. this applies to the stpclk cycle associated with c2 after pm14 is accessed. 3 reserved. 2:0 s45smaf. s4/s5 system management action eld. this applies to the stpclk cycle associated with s4 and s5 after pm04[slp_typ] is written with the either of these value. bits description 7:5 reserved. 4:3 c3s1lst. c3, s1 ldtstop_l assertion delay timer. see section 3.7.1.6 on page 57 for functional description of fon to c3 and fon to pos. (the times listed below are minimums, values up to 10% longer are within spec) c3s1lst time c3s1lst time 00b 1 microsecond 10b 64 microseconds 01b 32 microseconds 11b 128 microseconds 2:0 fvlst. frequency id/voltage id ldtstop_l timer. this eld speci es the minimum duration of ldtstop_l assertion when any of the following occur: a) acpi state transition for which ldtstop_l assertion is enabled, b) hypertransport technology system management vid/fid change request, c) ldtstop command through devb:3x78. the times shown below except fvlst=000b have a tolerance of +/ 10%. fvlst time fvlst time 000b 1 microseconds (min, +10%) 100b 16 microseconds 001b 2 microseconds 101b 32 microseconds 010b 4 microseconds 110b 64 microseconds 011b 8 microseconds 111b 128 microseconds 216registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information miscellanous register devb:3x75 default: 00h. attribute: read-write. link frequency change and resize ldtstop_l command register devb:3x78 default: (not applicable) attribute: write-only. system management device and subsystem id read-write register devb:3x7c default: 0000 0000h. attribute: read-write. read-write register devb:3x80 default: 0000h. attribute: read-write. bits description 7:0 must be low. read-write. these bits are required to be low at all times; if one bit is high then unde ned behavior results. bits description 31:1 reserved. 0 lscmd. ldtstop command. writing a 1 to this bit results in: (1) the ic generates a stpclk assertion with smaf bits as speci ed by devb:3x70[c3smaf], (2) upon receipt of the stop grant message, ldtstop_l is asserted for a period as speci ed by devb:3x74[fvlst], and (3) after the hypertransport link reconnects, the ic generates a stpclk deassertion message. bits description 31:16 ssid. subsystem id register. the value placed in this register is visible in devb:3x2c[31:16]. 15:0 ssvendorid. subsystem vendor id register. the value placed in this register is visible in devb:3x2c[15:0]. bits description 15:0 rw. read-write. these bits are read-write accessible through software; they control no hardware. chapter 4 registers 217 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information cardbus trap 1 and 2 i/o address register devb:3xb4 devb:3xb4, devb:3xb8, devb:3xbc, and devb:3xc0 combine to specify the address space for the cardbus0 and cardbus1 trap events. these events can be used to generate smis or scis, load the associated re-trigger timers (pm6c and pm70), or load the system inactivity timer. the cardbus0 and cardbus1 trap events occur when the following is true: cardbus0: ( (ad[15:0] | maskpio1 == addrpio1 | maskpio1) & (pci io access) ) | ( (ad[31:10] | maskpme1 == addrpme1 | maskpme1) & (pci mem access) ); cardbus1: ( (ad[15:0] | maskpio2 == addrpio2 | maskpio2) & (pci io access) ) | ( (ad[31:10] | maskpme2 == addrpme2 | maskpme2) & (pci mem access) ); where ad is the address ?ld of the host transaction. the mask bits for the i/o addresses cover bits[7:0]. the mask bits for the memory addresses cover bits[17:10]. default: 0000 0000h. attribute: read-write. pcmcia trap 1 memory address registers devb:3xb8 default: 0000 0000h. attribute: read-write. pcmcia trap 2 memory address registers devb:3xbc default: 0000 0000h. attribute: read-write. bits description 31:16 addrpio2. i/o address for the cardbus1 trap event . 15:0 addrpio1. i/o address for the cardbus0 trap event . bits description 31:10 addrpme1. memory address for the cardbus0 trap event . see devb:3xb4 for details. 9:0 reserved. bits description 31:10 addrpme2. memory address for the cardbus1 trap event . see devb:3xb4 for details. 9:0 reserved. 218 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information pcmcia trap mask registers devb:3xc0 default: 0000 0000h. attribute: read-write. programmable i/o range monitor 1 and 2 trap address register devb:3xc4 devb:3xc4, devb:3xc8, and devb:3xcc combine to specify the address space for programmable i/ o range monitor trap events (piorm[4:1]). these events can be used to generate smis or scis, load the associated re-trigger timer (pm78, pm7c, pm80, and pm84), or load the system inactivity timer. the trap events occurs following equations are true: piorm1:(ad[15:0] | maskio1 == addrio1 | maskio1); piorm2:(ad[15:0] | maskio2 == addrio2 | maskio2); piorm3:(ad[15:0] | maskio3 == addrio3 | maskio3); piorm4:(ad[15:0] | maskio4 == addrio4 | maskio4); where ad is the address ?ld a host i/o cycle. the mask bits cover any combination of bits[7:0]. default: 0000 0000h. attribute: read-write. programmable i/o range monitor 3 and 4 trap address register devb:3xc8 default: 0000 0000h. attribute: read-write. bits description 31:24 maskpme2. address mask for the pcmcia trap events . see devb:3xb4 for details. 23:16 maskpme1. address mask for the pcmcia trap events . see devb:3xb4 for details. 15:8 maskpio2. address mask for the pcmcia trap events . see devb:3xb4 for details. 7:0 maskpio1. address mask for the pcmcia trap events . see devb:3xb4 for details. bits description 31:16 addrio2. address for the piorm2 trap event . 15:0 addrio1. address for the piorm1 trap event . bits description 31:16 addrio4. address for the piorm4 trap event . see devb:3xc4 for details. 15:0 addrio3. address for the piorm3 trap event . see devb:3xc4 for details. chapter 4 registers 219 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information programmable i/o range monitor trap mask register devb:3xcc default: 0000 0000h. attribute: read-write. programmable memory/con guration range monitor 1 trap address register devb:3xd0 devb:3xd0, devb:3xd4, and devb:3xd8 combine to specify the address space for the programmable memory or con?uration space range monitor 1 and 2 trap events (pmemrm[1,2]). these events can be used to generate smis or scis, load the associated re-trigger timers (pm88 and pm8c), or load the system inactivity timer. these trap events occur when the following equations are true: pmemrm1: (ad[31:2] | maskmem1 == addrmem1[31:2] | maskmem1) & memsp & ~cfgspen1 | (ad[15:2] | maskmem1 == addrmem1[15:2] | maskmem1) & cfgsp & cfgspen1 & ~ad[24] & ~addrmem1[24] | (ad[23:2] | maskmem1 == addrmem1[23:2] | maskmem1) & cfgsp & cfgspen1 & ad[24] & addrmem1[24]; pmemrm2: (ad[31:2] | maskmem2 == addrmem2[31:2] | maskmem2) & memsp & ~cfgspen2 | (ad[15:2] | maskmem2 == addrmem2[15:2] | maskmem2) & cfgsp & cfgspen2 & ~ad[24] & ~addrmem2[24] | (ad[23:2] | maskmem2 == addrmem2[23:2] | maskmem2) & cfgsp & cfgspen2 & ad[24] & addrmem1[24]; where ad is the address ?ld of a host transaction, memsp indicates a memory space transaction and cfgsp indicates a con?uration space transaction. the mask bits cover address bits[17:2]. note that for con?uration traps, ad[24] and addrmem[2,1][24] carry the determination of whether the trap is a type 0 or type 1 con?uration cycle; if it is type 0, then the bus number bits are ignored. default: 0000 0000h. attribute: read-write. bits description 31:24 maskio4. address masks for the piorm4 trap events . see devb:3xc4 for details. 23:16 maskio3. address masks for the piorm3 trap events . see devb:3xc4 for details. 15:8 maskio2. address masks for the piorm2 trap events . see devb:3xc4 for details. 7:0 maskio1. address masks for the piorm1 trap events . see devb:3xc4 for details. bits description 31:2 addrmem1. memory address for the pmemrm1 trap event . 1 reserved. 0 cfgspen1. con guration space enable 1. 1=pmemrm1 is a con guration space trap. 0=pmemrm1 is a memory space trap. 220 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information programmable memory/con guration range monitor 2 trap address register devb:3xd4 default: 0000 0000h. attribute: read-write. programmable memory/con guration range monitor trap mask registers devb:3xd8 default: 0000 0000h. attribute: read-write. 4.7.2 system management i/o mapped registers (pmxx) these registers are located in i/o space. the base address registers for these registers is devb:3x58. see section 4.1.2 on page 136 for a description of the register naming convention. power management 1 status register (acpi pm1a_sts) pm00 each of these bits are status bits set by hardware events. most have the ability to generate an sci/smi interrupt, if they are enabled to do so in pm02. default: 0000h. attribute: read; set by hardware; write 1 to clear. bits description 31:2 addrmem2. memory address for the pmemrm2 trap event . see devb:3xd0 for details. 1 reserved. 0 cfgspen2. con guration space enable 2. 1=pmemrm2 is a con guration space trap. 0=pmemrm2 is a memory space trap. see devb:3xd0 for details. bits description 31:16 maskmem2. address mask for the pmemrm2 trap event . see devb:3xd0 for details. 15:0 maskmem1. address mask for the pmemrm1 trap event . see devb:3xd0 for details. bits description 15 wak_sts. wake status. this bit is set by hardware when the system is in any sleep state (pos, str, std, or soff) and an enabled resume event occurs. upon setting this bit, the system resumes. 14:12 reserved. 11 pbor_sts. power button override status. this bit is set by hardware when a power button override event occurs. a power button override event occurs if pm26[pbor_dis] is low and pwrbtn_l is held in the active state for more than four seconds or if pm26[sbor_dis] is low, the slpbtn_l function is enabled by pmd7, and slpbtn_l is held in the active state for more than four seconds. this bit resides on the vdd_corex power plane. 10 rtc_sts. real-time clock status. this bit is set by hardware when the real-time clock generates an interrupt. this bit resides on the vdd_corex power plane. chapter 4 registers 221 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information power management 1 enable register (acpi pm1a_en) pm02 most of these bits work in conjunction with the corresponding sts bits in pm00 to generate sci or smi interrupts (based on the state of pm04[sci_en]). default: 0100h. attribute: read-write. 9 slpbtn_sts. sleep button status. 1=indicates that the sleep button (slpbtn_l) has been asserted. the debounce circuitry causes a 12-to-16 millisecond delay from the time the input signal stabilizes until this bit changes. if the gpio debounce circuitry speci ed by pmd7 is enabled, then the debounce period is twice as long before setting the status bit. if the slpbtn_l function is not selected by pmd7, then this bit is not set. if pm26[sbor_dis] is low and slpbtn_l is held low for more than four seconds, then this bit is cleared and pbor_sts is set. this bit resides on the vdd_corex power plane. note: the debounce circuit functions in the high-to-low and low-to-high directions. 8 pwrbtn_sts. power button status. 1=indicates that the power button (pwrbtn_l) has been asserted. the debounce circuitry causes a 12-to-16 millisecond delay from the time the input signal stabilizes until this bit changes. if pm26[pbor_dis] is low and pwrbtn_l is held low for more than four seconds, then this bit is cleared and pbor_sts is set. this bit resides on the vdd_corex power plane. note: the debounce circuit functions in the high-to-low and low-to-high directions. 7:6 reserved. 5 gbl_sts. global status. this bit is set by hardware when a 1 is written to pm2c[bios_rls]. 4 bm_sts. bus master status. this bit is set by hardware when a secondary pci bus request signal becomes active, ldtreq_l is asserted, or any internal source requests access to the host. based on the state of pm04[bm_rld], this may result in a power state transition. note: this bit is not set by hypertransport technology system management messages, hypertransport interrupt requests, and hypertransport fence or ush commands. 3:1 reserved. 0 tmr_sts. acpi timer status. this bit is set by hardware when the msb (either bit 23 or 31 based on devb:3x41[3]) of the acpi timer (pm08) toggles (from 0 to 1 or 1 to 0). bits description 15:11 reserved. 10 rtc_en. real-time clock alarm sci/smi enable. 1=enable an sci or smi interrupt when pm00[rtc_sts] is set high. this bit resides on the vdd_corex power plane. 9 slpbtn_en. sleep button sci/smi enable. 1=enable an sci or smi interrupt when pm00[slpbtn_sts] is set high. this bit resides on the vdd_corex power plane. 8 pwrbtn_en. power button sci/smi enable. 1=enable an sci or smi interrupt when pm00[pwrbtn_sts] is set high. this bit resides on the vdd_corex power plane. 7:6 reserved. 5 gbl_en. global sci enable. 1=enable an sci interrupt when pm00[gbl_sts] is set high. note: this results in an sci interrupt, regardless as to the state of pm04[sci_en]. 4:1 reserved. 0 tmr_en. acpi timer sci enable. 1=enable an sci interrupt when pm00[tmr_sts] is set high. note: this results in an sci interrupt, regardless as to the state of pm04[sci_en]. bits description 222 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information power management 1 control register (acpi pm1_cnta) pm04 default: 0000h. attribute: see below. acpi power management timer (acpi pm_tmr) pm08 this is either a 24- or a 32-bit counter, based on the state of devb:3x41[3]. it is a free-running, incrementing counter clocked off of a 3.579545 mhz. clock. it does not count when in the system is in moff, soff, std, or str state. when the msb toggles (either bit[23] or bit[31]) then pm00[tmr_sts] is set. this timer is asynchronously cleared when devb:3x41[tmrrst] is high. default:0000 0000h. attribute: read-only. bits description 15:14 reserved. 13 slp_en. sleep enable. write-only; reads back as 0. writing a 1 to this bit causes the system to sequence into the sleep state speci ed by slp_typ. 12:10 slp_typ. sleep type. read-write. speci es the type of sleep state the system enters when slp_en is set high. 0 fon, s0. full on. 1 pos, s1. power on suspend. power state transition speci ed by devb:3x50. 2-4 reserved. 5 str, s3. suspend to ram. 6 std, s4. suspend to disk. 7 soff, s5. soft off. 9:3 reserved. 2 gbl_rls. global release. read; write 1 only; cleared by hardware. when this bit is set high, the hardware sets pm28[bios_sts] high. gbl_rls is cleared by the hardware when pm28[bios_sts] is cleared by software. 1 bm_rld. bus master reload. read-write. 1=enables the transition of the processor power state from c3 to c0 to be triggered by any bus master requests or hypertransport source link requests (when pm00[bm_sts] is set). 0 sci_en. sci-smi select. read-write. selects the type of interrupt generated by power management events. 0=smi interrupt. 1=sci interrupt. note that certain power management events can be programmed individually to generate smi interrupts independent of the state of this bit. see section 3.7.1.1 on page 54 for details. also, tmr_sts and gbl_sts always generate sci interrupts regardless as to the state of this bit. bits description 31:24 etm_val. extended timer value. if devb:3x41[3] is high, then these are the 8 msbs of the acpi power management timer. if devb:3x41[3] is low, then this eld always reads back as all zeros. 23:0 tmr_val. timer value. read-only. this eld returns the running count of the acpi power management timer. chapter 4 registers 223 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information processor clock control register (acpi p_cnt) pm10 default: 0000 0000h. attribute: read-write. processor level 2 register (acpi p_lvl2) pm14 default: 00h. attribute: read-only. processor level 3 register (acpi p_lvl3) pm15 default: 00h. attribute: read-only. power management control register pm1c default: 00h. attribute: read-write. bits description 31:5 reserved. 4 nth_en. normal throttling enable. 1=normal throttling (duty cycle speci ed by nth_ratio) is enabled. normal throttling is disabled when thermal throttling. 0=normal throttling is not enabled. 3:1 nth_ratio. normal throttling duty cycle. these bits specify the duty cycle of the stpclk_l pin when the system is in normal throttling mode, enabled by nth_en. the eld is decoded as follows: nth_ratio description nth_ratio description 0h reserved 4h 50.0% in stop grant state 1h 87.5% in stop grant state 5h 37.5% in stop grant state 2h 75.0% in stop grant state 6h 25.0% in stop grant state 3h 62.5% in stop grant state 7h 12.5% in stop grant state 0 reserved. bits description 7:0 p_lvl2. reads from this register place the processor into the c2 power state, as speci ed by devb:3x4f. reads from this register always return 00h. this register is byte readable only. bits description 7:0 p_lvl3. reads from this register place the processor into the c3 power state, as speci ed by devb:3x4f. reads from this register always return 00h. this register is byte readable only. bits description 7:1 reserved. 0 arb_dis. arbiter disable. 1=disable all secondary pci masters from being granted the bus and all internal hypertransport sources from initiating memory space transactions. this is in support of the acpi c3 state in which the processor is not capable of supporting snoops. 0=enable. 224 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information software smi trigger register pm1e (pm2f) default: 00h. attribute: read-write. fan rpm count register pm1f default: 00h. attribute: read-only. general purpose 0 status register (acpi gpe0_sts) pm20 most of the bits in this register may be enabled to generate sci or smi interrupts (based on the state of pm04[sci_en]) through pm22 or may be enabled to generate smi interrupts through pm2a and pm2c. default: 0000h. attribute: read; set by hardware; write 1 to clear. bits description 7:0 this address accesses the same physical register located at pm2f. i.e., both accesses to pm1e and pm2f identically access the same register and both can be used to set pm28[swi_sts]. bits description 7:0 rpmcnt. fanrpm count register. this provides the state of a counter that increments on every rising edge of the signal fanrpm. if the fanrpm function is not selected by pmca, then this register does not change. bits description 15 usbrsm_sts. usb-de ned resume event status. this bit is set high by the hardware when a usb-de ned resume event has occurred from either usb controller. this bit resides on the vdd_corex power plane. 14 ri_sts. ri_l pin status. this bit is set high by the hardware when the ri_l pin is asserted. this bit resides on the vdd_corex power plane. 13 lid_sts. lid status. this bit is set high by the hardware when the lid signal has changed state indicating that the lid has either opened or closed. this bit resides on the vdd_corex power plane. 12 acav_sts. ac change status. this bit is set high by the hardware when the acav signal has changed state indicating that ac power has either been added or removed from the system. this bit resides on the vdd_corex power plane. note: the default value of this bit (from moff) is indeterminate. 11 smbus_sts. smbus status. this bit is set high if an smbus status bit in pme0[snp_sts, hslv_sts, and smba_sts] is high while enabled by pme2[snp_en, hslv_en, and smba_en], respectively, or if any of pme0[abrt_sts, col_sts, prerr_sts, hcyc_sts, to_sts] are set high while enabled by pme2[hcyc_en]. note: only pme0[smba_en, hslv_sts, snp_sts] can be enabled to wake the system out of sleep states. this bit resides on the vdd_corex power plane. 10 therm_sts. therm_l pin status. this bit is set high by the hardware when the therm_l pin is asserted. 9 extsmi_sts. external smi pin status. this bit is set high by the hardware when the extsmi_l pin is asserted. this bit resides on the vdd_corex power plane. chapter 4 registers 225 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information general purpose 0 acpi interrupt enable register (acpi gpe0_en) pm22 for each of the bits in this register: 1=enable a corresponding status bit in pm20 to generate an smi or sci interrupt (based on the state of pm04[sci_en]). 0=do not enable the smi or sci interrupt. default: 0000h. attribute: read-write. 8 pme_sts. pme_l pin status. this bit is set high by the hardware when the pme_l pin is asserted low. this bit may be set high by the pme function from the ethernet controller. this bit resides on the vdd_corex power plane. 7 tcosci_sts. tco sci interrupt status. this bit is set high by the hardware when there is a 0 to 1 transition on pm46[intrdr_sts] or pm44[tco_int_sts]. 6 reserved. 5 sit_sts. system inactivity timer time out status. this bit is set high by the hardware when the system inactivity timer times out. 4 reserved. 3 smbc_sts. smbus controller system management event. this bit is set high by the smbus controller. this bit resides on the vdd_corex power plane. 2 reserved. software should ignore this bit. 1 ac97_sts. ac 97 wake event status. this bit is set high by the hardware when the ac 97 link generates a wake event. this bit resides on the vdd_corex power plane. this bit is also set if ac30/mc40[gpiint] is 1 . 0 dm_sts. hardware device monitor (parent) event status. this bit is set high by the hardware when any of the device monitor event status bits in pma0 become active when enable by the corresponding bits in pma4. bits description 15 usbrsm_en. usb resume event acpi interrupt enable . this bit resides on the vdd_corex power plane. 14 ri_en. ri_l pin acpi interrupt enable . this bit resides on the vdd_corex power plane. 13 lid_en. lid pin acpi interrupt enable . this bit resides on the vdd_corex power plane. 12 acav_en. acav pin acpi interrupt enable . this bit resides on the vdd_corex power plane. 11 smbus_en. smbus (parent) acpi interrupt enable . this bit resides on the vdd_corex power plane. 10 therm_en. therm_l pin acpi interrupt enable. 9 extsmi_en. external smi pin acpi interrupt enable. this bit resides on the vdd_corex power plane. 8 pme_en. pme_l pin acpi interrupt enable . this bit resides on the vdd_corex power plane. 7 tcosci_en. tco sci enable . note: when this is high, devb:3x44[tco_int_sel] is ignored. 6 reserved. 5 sit_en. system inactivity timer time out acpi interrupt enable . 4 reserved. bits description (continued) 226registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information sleep state resume enable register pm26 all the bits in this register reside in the vdd_corex power plane. default: 2000h. attribute: read-write. 3 smbc_en. smbus controller acpi interrupt enable . this bit resides on the vdd_corex power plane. 2 reserved . software should only write 0 to this bit. 1 ac97_en. ac 97 wake event acpi interrupt enable . this bit resides on the vdd_corex power plane. 0 dm_en. device monitor (parent) acpi interrupt enable . bits description 15 batlow_ctl. battery low enable control. 1=enable batlow_l assertion to prevent a system resume from any sleep state (pos, std, str, or soff) if pmc0 enables acav functionality and the acav input is low or if pmc0 disables acav functionality. all resume events except that associated with acav_sts are affected by this bit. 14 minsleep. minimum sleep time. 1=the minimum time in which pwron_l is deasserted in support of str, std, or soff is 500 to 800 milliseconds. i.e., resume events that occur shortly after entry into these sleep states are not acted upon until this minimum time has transpired. 0=there is no minimum time in which pwron_l is deasserted. 13 sbor_dis. slpbtn_l override disable. 1=the power button override event from the slpbtn_l pin (holding slpbtn_l active for four seconds) does not set pm00[pbor_sts] high and does not automatically transition the system into soff. 0=the power button override event from the slpbtn_l pin is enabled to set pm00[pbor_sts] high and place the system into the soff mode. 12 reserved. 11 pbor_dis. power button override disable. 1=the power button override event (holding pwrbtn_l active for four seconds) does not set pm00[pbor_sts] high and does not automatically transition the system into soff. 0=the power button override event is enabled to set pm00[pbor_sts] high and place the system into the soff mode. 10:0 reserved. bits description chapter 4 registers 227 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information global status register pm28 each of the evt bits specify smi-interrupt-enabled status bits in other registers. these are not sticky bits; they re?ct the combinatorial equation of: _evt = (status1 & smi enable1) | (status2 & smi enable2)... default: 0000h. attribute: see below. bits description 15 misc_evt. miscellaneous smi event. read-only. this bit is read as 1 when there are set status bits in pm30 that are enabled in pm32. 14 reserved. 13 gpe0_evt. general purpose event 0 event status. read-only. this bit goes high when any of the pm20 status bits that are smi enabled by pm2a or pm2c become active (this does not include pm20[dm_sts]). note: pm20[tcosci_sts] is not included. 12 usb_evt. usb smi event. read-only. this bit is read as 1 when one of the usb-de ned smi events occurs in either usb controller. this occurs when hccontrol[8] is high and an enabled interrupt occurs (hcinterruptstatus and hcinterruptcontrol). this bit is not affected by pm20[usbrsm_sts]. 11 smbus_evt. smbus event status. read-only. this bit is read as 1 when an smbus status bit in pme0[snp_sts, hslv_sts, and smba_sts] is high while enabled by pme2[snp_en, hslv_en, and smba_en], respectively, or when any of pme0[abrt_sts, col_sts, prerr_sts, hcyc_sts, to_sts] are set high while enabled by pme2[hcyc_en]. 10:8 reserved. 7 swi_sts. software smi status. read; set by hardware; write 1 to clear. this bit is set high by the hardware when a write of any value is sent to pm1e or pm2f. this bit can trigger smi interrupts if enabled by pm2a[swismi_en]. 6 bios_sts. bios status. read; set by hardware; write 1 to clear. this bit is set high by the hardware when pm04[gbl_rls] is set high. bios_sts is cleared when a 1 is written to it; writing a 1 to bios_sts also causes the hardware to clear pm04[gbl_rls]. this bit can trigger smi interrupts if enabled by pm2a[biossmi_en]. 5 reserved. 4 irqrsm_sts. irq resume status. read; set by hardware; write 1 to clear. 1=system was resumed from pos due to an unmasked interrupt assertion and pm2a[irq_rsm] is high. 0=system was not resumed from pos due to an interrupt. note: this bit is set only by resumes from pos. note: devb:3x50[pitrsm_l, msrsm_l] can be set to inhibit timer tick and mouse interrupts during pos. 3 gpio_evt. gpio interrupt status. read-only. this bit is read as 1 when any of the general purpose i/o status bits in pmb0 that are smi enabled by pmb8 become active. 2 pm1_evt. power management 1 status. read-only. this bit is read as 1 when any of the status bits in pm00 are active (they do not need to be enabled by pm02). 1 tco_evt. tco smi interrupt event. read-only. this bit is read as 1 when any of pm44[nmi2smi_sts, sw_tco_smi, tout_sts, ibios_sts] are set. 0 dm_evt. hardware device monitor event status. read-only. this bit is read as 1 when any of the device monitor status bits in pma0 that are smi enabled by pma8 become active. 228 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information global smi enable register pm2a most of these bits enable the status bits to generate smi interrupts. for each of these bits: 1=enable the corresponding sts bit in the speci?d register to generate an smi interrupt, regardless as to the state of pm04[sci_en]. default: 0000h. attribute: read-write. global smi control register pm2c default: 0000h. attribute: see below. bits description 15 usbsmi_en. usb resume smi enable. generate smi when pm20[usbrsm_sts]=1. 14 rismi_en. ri_l pin smi enable. generate smi when pm20[ri_sts]=1. 13 sbsmi_en. slpbtn_l pin smi enable. generate smi when pm00[slpbtn_sts]=1. 12 pbsmi_en. pwrbtn_l pin smi enable. generate smi when pm00[pwrbtn_sts]=1. 11 smbsmi_en. smbus event smi enable. generate smi when pm28[smbus_evt]=1. 10 thmsmi_en. therm_l pin smi enable. generate smi when pm20[therm_sts]=1. 9 extsmi_en. external smi pin smi enable. generate smi when pm20[extsmi_sts]=1. 8 pmesmi_en. pme_l pin smi enable. generate smi when pm20[pme_sts]=1. 7 swismi_en. software smi enable. generate smi when pm28[swi_sts]=1. 6 biossmi_en. bios smi enable. generate smi when pm28[bios_sts]=1. 5 sitsmi_en. system inactivity timer time out smi enable. generate smi when pm20[sit_sts]=1. 4 irq_rsm. resume from pos on unmasked interrupt. 1=enable resume from pos when pm28[irqrsm_sts] is set high. 3 bmsmi_en. bus master smi enable. generate smi when pm00[bm_sts]=1. 2 lidsmi_en. lid pin smi enable. generate smi when pm20[lid_sts]=1. 1 tco_en. tco smi interrupt enable. generate smi when pm28[tco_evt]=1. note: if pm48[nmi2smi_en]=1, pm44[nmi2smi_sts] generates smi interrupts regardless of the state of this bit. even if the tco_en bit is 0, nmis are routed to generate smis. 0 acavsmi_en. acav pin smi enable. generate smi when pm20[acav_sts]=1. bits description 15:8 reserved. 7 smbcsmi_en. smbus controller system management event smi enable. read-write. 1=an smi is generated if pm20[smbc_sts] goes high. 6 reserved. software should only write a 0 to this bit. 5 smiact. smi active. read; set by hardware; write 1 to clear. this bit is set high by the hardware on the leading edge of the smi output. if smilk is high, then smiact holds the smi_l pin in the active state. if smilk is low, then smiact has no effect on the smi signal. 4 smilk. smi lock control. read-write. 1=the smi_l pin is locked into the active state by a latch after it is asserted. the latch is controlled by smiact. 0=the state of smiact does not affect smi_l. chapter 4 registers 229 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information advanced power management status register pm2e default: 00h. attribute: read-write. software smi trigger register pm2f default: 00h. attribute: read-write. miscellaneous smi status register pm30 these bits may be enabled to generate smi interrupts through pm32. default: 0000h. attribute: read; set by hardware; write 1 to clear. 3 eos. end of smi. write-only. writing a 1 to this bit forces the smi_l pin to be deasserted for 4 pci clocks. this bit always reads as a 0. 2 ac97smi_en. ac 97 wake event smi enable. read-write. 1=generate smi when pm20[ac97_sts] goes high. 1 bios_rls. bios sci/smi lock release. read; write 1 only; cleared by hardware. this bit is set high by software to indicate the release of the sci/smi lock. when this bit is set high, pm00[gbl_sts] is set high by the hardware. bios_rls is cleared by the hardware when pm00[gbl_sts] is cleared by software. note that if pm02[gbl_en] is set, then setting this bit generates an sci interrupt. 0 smi_en. smi enable control. read-write. 1=enable generation of smis from the system management logic (including all smi sources in the system management logic and the smi from the serial irq logic, but not smis from the ioapic). 0=disable smis from the system management logic (however, if smiact is set and smi_en is cleared, smi_l remains asserted until smiact is cleared). bits description 7:0 apm_status. this has no affect on hardware. this register may be used to pass status information between the os and the smi handler. bits description 7:0 smi_cmd. smi command. writes to this register set pm28[swi_sts]. if pm2a[swismi_en] is set, then writes to this port generate smi interrupts. reads of this register provide the data last written to it. this register is accessible pm1e as well. bits description 15:5 reserved. 4 64ms_sts. 64 millisecond timer status. after pm32[64ms_en] is set high, the 64 millisecond timer counts out 64 +/- 4 milliseconds and then sets this bit. the timer continues counting the next 64 millisecond period after this bit is set. 230 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information miscellaneous smi enable register pm32 for each of the bits in this register: 1=enable a corresponding status bit in pm30 to generate an smi interrupt. 0=do not enable the smi interrupt. default: 0000h. attribute: read-write. tco timer reload and current value register pm40 the tco timer is a decrementing counter that is clocked approximately every 0.6 seconds providing times of up to 38 seconds. if it decrements past zero, it sets pm44[tout_sts], rolls over to the value in pm41, and keeps counting. default: 04h. attribute: read; write command. 3 1min_sts. one minute status bit. after entering the fon state, this bit is set every 60 +/- 4 seconds. 2 sirqsmi_sts. serial irq smi status. this bit is set an smi is transferred into the ic through the serial irq. 1 rwr_sts. bios rom write enable status. this bit is set when devb:0x40[rwr] is written from a 0 to a 1. 0 slpcmd_sts. this bit is set if there is a write of pm04[slp_en] to a high. bits description 15:5 reserved. 4 64ms_en. 64 millisecond smi enable. 1=enable the 64 millisecond counter, as well as the corresponding smi interrupt. 0=the 64 millisecond timer is cleared. 3 1min_en. one minute smi enable . 2 sirqsmi_en. serial irq smi enable . 1 rwr_en. bios rom write enable smi enable. read, write to 1 only. once this bit is set, it can only be cleared by reset_l. 0 slpcmd_en. enable smi on sleep command. note: when this bit is set high and the sleep command is sent to pm04, the system power state is disabled from changing. it is expected that the smi interrupt service routine will clear pm30[slpcmd_sts], clear this bit, and then re-issue the command in order to change the system power state. bits description 7:6 reserved. 5:0 tcorld. tco timer. reads of this register return the current count of the tco timer. writes of any value to this register cause the tco timer to be reloaded with the value in pm41. chapter 4 registers 231 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information tco timer initial value register pm41 default: 04h. attribute: read-write. tco smi data in register pm42 default: 00h. attribute: read-write. tco smi data out register pm43 default: 00h. attribute: read-write. tco status 1 register pm44 default: 0000h. attribute: read; set by hardware; write 1 to clear. bits description 7:6 reserved. 5:0 tcotime. tco timer reload value. speci es the value to be loaded into the tco timer, pm40. bits description 7:0 tcosmi. tco smi data. writes to this register set pm44[sw_tco_smi] and generate an smi. bits description 7:0 tcoout. tco output data to os. writes to this register set pm44[tco_int_sts] and generate an irq as speci ed by devb:3x44[tco_int_sel] and pm22[tcosci_en]. bits description 15:9 reserved. 8 ibios_sts. bios illegal access status. 1=hardware sets this bit and an smi is generated (if pm2a[tco_en]=1) as a result of an illegal access to bios address space; this occurs when: (1) there is a read to a read-locked address or a write to a write-locked address as speci ed by devb:0x40[rwr], devb:0x80, devb:0x84, devb:0x88, and devb:0x8c[3:0] or (2) devb:0x40[ble]=1 and devb:0x40[rwr] is written from a 0 to a 1. 7:4 reserved. 3 tout_sts. tco timer timeout status. 1=hardware sets this bit and an smi is generated (if pm2a[tco_en]=1) as a result of the tco timer (pm40) counting past zero. 2 tco_int_sts. tco interrupt status. 1=hardware sets this bit and an irq is generated (as speci ed by devb:3x44[tco_int_sel] and pm22[tcosci_en]) by a write to pm43. 1 sw_tco_smi. software-generated smi status. 1=hardware sets this bit and an smi is generated (if pm2a[tco_en]=1) by a write to pm42. 0 nmi2smi_sts. nmi to smi status. 1=hardware sets this bit and an smi is generated as a result of an nmi while pm48[nmi2smi_en] is high. note: pm48[nmi_now] does not set this status bit. 232 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information tco status 2 register pm46 default: 00h. attribute: read; set by hardware; write 1 to clear. tco control 1 register pm48 default: 0000h. attribute: read-write. tco control 2 register pm4a default: 00h. attribute: read-write. bits description 7:4 reserved. 3 tt_sts. thermtrip status. 1=thermtrip_l was asserted while pwron_l = 0, pwrok = 1, and reset_l = 1. this bit resides in the vdd_corex power plane. 2 boot_sts. boot status. 1=hardware sets this bit when pm46[2ndto_sts] changes from 0 to 1 after any reset_l before any rom accesses have occurred. this bit resides on the vdd_corex power plane. 1 2ndto_sts. second tco time out status. 1=hardware sets this bit when the tco timer, pm40, times out a second time before pm44[tout_sts] is cleared. if enabled by devb:3x48[no_reboot], this may trigger a reboot of the system. this bit resides on the vdd_corex power plane. 0 intrdr_sts. intruder detect status. 1=hardware sets this bit when the intruder_l pin is asserted for more than 60 microseconds (debounce time); this bit functions in all power states (unless al is not powered). this bit resides in the vdd_coreal power plane; when vdd_coreal is powered, this bit defaults to 0. this may trigger an interrupt as speci ed by pm4a[intrdr_sel]. bits description 15:12 reserved. 11 tcohalt. tco timer halt. 1=freeze the tco timer (pm40) in its current state; pm44[tout_sts] and pm46[2ndto_sts] cannot be set. 10 reserved. 9 nmi2smi_en. nmi interrupts generate smi interrupts. 1=whenever an nmi is detected, pm44[nmi2smi_sts] is set and no nmi is generated; this bit does not affect nmi_now (setting nmi_now generates an nmi regardless of the state of nmi2smi_en). note: if this bit is set and rtc70[nmidis] is set, then no nmis or associated smis are generated. 8 nmi_now. generate nmi. 1=generate nmi. it is expected that the nmi handler clears this bit. 7:0 reserved. bits description 7:3 reserved. 2:1 intrdr_sel. select the action to take if pm46[intrdr_sts] is set. 00b=reserved; 01b=irq (as speci ed by devb:3x44[tco_int_sel]); 10b=smi; 11b=reserved. 0 reserved. chapter 4 registers 233 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information read write register pm4c all these bits reside on the vdd_corex power plane. default: 0000h. attribute: read-write. timer and device monitor registers pm[8c:50] bits[19:0] each of these registers provide access to the re-trigger timers. each timer decrements at a rate speci?d by clksrc when enabled. each timer is associated with device monitor events including address traps, dma acknowledge cycles and interrupt requests. each time a device monitor event associated with a re-trigger timer occurs, the timer is reloaded. so, if the hardware is regularly accessed, then the timer never reaches zero. if the timer decrements past zero, then it is disabled from counting further (staying at zero) and the appropriate device monitor status bit is set. here is a summary of the device monitor events associated with these registers: bits description 31:24 reserved. 23:0 rw. these bits control no hardware. table 58. device monitor events register function address specification; dma channels; irqs pm50 access to the primary or secondary oppy disk controllers. i/o space 3f0h-3f5h, 3f7h, or 370h-375h, 377h xed; dma channel 2 in pm50 pm54 1 access to the parallel ports. see pm54; one of dma[3:0]; see note. pm58 access to serial port coma. (modem) see pm58 pm5c access to serial port comb. (ir) see pm5c pm60 access to the audio hardware. see pm60; any or all or dma[7:5, 3:0] pm64 user interface: access to the video adapter; access to the legacy keyboard and ps/2 mouse ports; pci bus utilization memory space 0a0000h-0bffffh xed; i/o space 3b0h-3dfh, 60h, 64h; irq1, irq12 pm68 pio access to any ide drives. i/o address space speci ed by devb:1xxx pm6c access to cardbus 0. address in space devb:3xb4, devb:3xb8, pm70 access to cardbus 1. devb:3xbc, devb:3xc0 pm74 timer. none. pm78 access to programmable i/o range monitor 1. address in space devb:3xc4, devb:3xc8, pm7c access to programmable i/o range monitor 2. devb:3xcc pm80 access to programmable i/o range monitor 3. pm84 access to programmable i/o range monitor 4. pm88 access to programmable memory/con g range monitor 1. address in space devb:3xd0, devb:3xd4, pm8c access to programmable memory/con g range monitor 2. devb:3xd8 notes: 1. pm54 can alternately be used as an inactivity timer for pci bus master activity based on req_l[6:0], preq_l, and internal master requests. 234 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information the following provides the ?ld de?itions for bits[19:0] common to each of the sixteen 32-bit registers from pm50 to pm8c. see pm50-pm8c bits[31:20], below, for the unique bit de?itions. default: 0000h (for each register). attribute: see below. offset: 8fh-40h (four bytes for each register). floppy disk controller device monitor unique controls pm50 bits[31:20] see pm[8c:50], above, for bits[19:0]. default: 0000 0000h. attribute: read-write. bits description 31:20 see pm50-pm8c below 19 reserved. 18 tmr_en. re-trigger timer enable. read-write. 1=enable the re-trigger timer to decrement and to set the corresponding bit in the device monitor status register (pma0) to generate an smi or sci interrupt. 0=disable. if the timer is enabled and decrements past zero, then the pma0 status bit is set and the timer stops (at zero). also, whenever a high is written to tmr_en, the corresponding re- trigger timer is loaded with its reload value. 17 sit_rld. system inactivity timer reload on device monitor event. read-write. 1=enable system inactivity timer (pm98) to be reloaded by associated device monitor events; the event (not the associated sts bit) causes the sit to be reloaded. 0=sit not reloaded by associated device monitor event. 16 reserved. 15:14 clksrc. clock source. read-write. speci es the clock to the re-trigger timer per the following table. clksrc clock period maximum time (clock times 128) 00b 1 millisecond 128 milliseconds 01b 32 milliseconds 4.1 seconds 10b 1 second 128 seconds = 2.13 minutes 11b 64 seconds 136.5 minutes = 2.28 hours 13:7 curcount. re-trigger timer current count value . read-only. 6:0 reload. re-trigger timer reload value. read-write. device monitor events cause the re-trigger timer to be loaded with the state of this register. also, writes to this eld cause the re-trigger counter curcount to be updated. bits description 31:23 reserved. 22 fdcdec_en. floppy disk controller decode enable. 1=enable accesses to oppy disk controller address range speci ed by pm50[fdcdec_sel] to generate a device monitor event. 0=disable. 21 fdcdec_sel. floppy disk controller decode select. this selects the oppy disk controller i/o address range for the fdc device monitor events. 1=secondary fdc address (370h-375h, 377h). 0=primary fdc address (3f0h-3f5h, 3f7h). 20 fdcdma_en. floppy disk controller dma enable. 1=enable dma channel 2 to generate the fdc device monitor event. 0=disable. chapter 4 registers 235 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information parallel port device monitor unique controls pm54 bits[31:20] see pm[8c:50], above, for bits[19:0]. default: 0000 0000h. attribute: read-write. bits description 31:27 reserved. 26 bmit_en. bus master inactivity timer enable. 1=re-trigger timer associated with pm54 is reloaded whenever a master access is indicated by req_l[6:0], preq_l, or internal masters. 0=re- trigger timer associated with pm54 is reloaded by parallel port device monitor events speci ed by lptdec_en and lptdma_en. 25 lptdec_en. lpt port monitoring enable. 1=enable accesses to the i/o address range selected by pm54[lptdec_sel] to generate a parallel port device monitor event. 24:23 lptdec_sel. lpt controller decode select. selects the i/o address range used for parallel port device monitor events. bits[24:23] lpt decode 00 3bch 3bfh, 7bch 7beh 01 378h 37fh, 778h 77ah 10 278h 27fh, 678h 67ah 11 reserved 22 lptdma_en. lpt dma enable. 1=enable the dma channel selected by pm54[lptdma_sel] to generate a parallel port device monitor event. 21:20 lptdma_sel. lpt dma select. selects the dma channel used for the parallel port device monitor event. bits[21:20] dma channel 00 dma channel 0 01 dma channel 1 10 dma channel 3 11 reserved 236registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information serial port a device monitor unique controls pm58 bits[31:20] see pm[8c:50], above, for bits[19:0]. default: 0000 0000h. attribute: read-write. serial port b and audio device monitor unique controls pm5c bits[31:20] see pm[8c:50], above, for bits[19:0]. note: bits[31:24] of this register apply to the audio device monitor controls at pm60. default: 0000 0000h. attribute: read-write. bits description 31:24 reserved. 23 cmadec_en. serial port a monitor enable. 1=enable accesses to the i/o address range selected by pm58[cmadec_sel] to generate a serial port a device monitor event. 22:20 cmadec_sel. serial port a decode select. selects the i/o address range used for serial port a device monitor events. bits[22:20] serial a decode bits[22:20] serial a decode 000 3f8h 3ffh (com1) 100 238h 23fh 001 2f8h 2ffh (com2) 101 2e8h 2efh (com4) 010 220h 227h 110 338h 33fh 011 228h 22fh 111 3e8h 3efh (com3) bits description 31:29 reserved. 28 mss_en. microsoft sound system decode enable. 1=enable accesses to the i/o address range selected by pm5c[mss_sel] to generate an audio device monitor event. note: this bit applies to the audio device monitor, pm60. 27:26 mss_sel. microsoft sound system decode select. selects the mss i/o address range used for audio device monitor events. note: this bit applies to the audio device monitor, pm60. bits[4:3] mss decode 00 530h 537h 01 604h 60bh 10 e80h e87h 11 f40h f47h chapter 4 registers 237 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information audio device monitor unique controls pm60 bits[31:20] see pm[8c:50], above, for bits[19:0]. note: pm5c[31:24] contains some control bits for the audio device monitors as well as pm60. default: 0000 0000h. attribute: read-write. 25 game_en. game port enable. 1=enable accesses to the i/o address range 200h-207h to generate audio device monitor events. note: this bit applies to the audio device monitor, pm60. 24 midi_en. midi enable. 1=enable accesses to the i/o address range selected by pm60[midi_sel] to generate an audio device monitor event. note: this bit applies to the audio device monitor, pm60. 23 cmbdec_en. serial port b monitor enable. 1=enable accesses to the i/o address range selected by pm5c[cmbdec_sel] to generate a serial port b device monitor event. 22:20 cmbdec_sel. serial port b decode select. selects the i/o address range used for serial port b device monitor events. bits[22:20] serial b decode bits[22:20] serial b decode 000 3f8h 3ffh (com1) 100 238h 23fh 001 2f8h 2ffh (com2) 101 2e8h 2efh (com4) 010 220h 227h 110 338h 33fh 011 228h 22fh 111 3e8h 3efh (com3) bits description 31:30 midi_sel. midi decode select. selects the midi i/o range used for audio device monitor events (the enable for this range is pm5c[midi_en]). bits [31:30] midi decode 00 300h 303h 01 310h 313h 10 320h 323h 11 330h 333h bits description (continued) 238 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information user interface device monitor unique controls pm64 bits[31:20] see pm[8c:50], above, for bits[19:0]. default: 0000 0000h. attribute: read-write. 29 reserved. 28 sb_en. sound blaster 8/16 decode enable. 1=enable accesses to the i/o address range selected by the sb_sel eld and to 388h-38bh to generate audio device monitor events. 27:26 sb_sel. sound blaster decode select. selects the sound blaster i/o address range used for audio device monitor events. bits [27:26] sb_sel decode 00 220h 233h 01 240h 253h 10 260h 273h 11 280h 293h 25:20 adma_en. audio dma enable. each of these bits speci es whether a dma channel is enabled for audio device monitor events. bit[20] speci es dma channel 0; bit[21] speci es dma channel 1; bit[22] speci es dma channel 3; bit[23] speci es dma channel 5; bit[24] speci es dma channel 6; bit[25] speci es dma channel 7. 1=enable the corresponding dma request signal to generate an audio device monitor event. 0=disable. bits description 31:25 reserved. 24 grab_en. graphics a/b segment memory enable. 1=enable accesses to vga frame buffer memory address ranges a_0000h through b_ffffh to generate user interface device monitor events. 23 grio_en. graphics i/o enable. 1=enable accesses to vga i/o addresses 3b0h-3dfh to generate user interface device monitor events. 22 kbc_en. keyboard enable. 1=enable accesses to the keyboard controller i/o address range (ports 60h and 64h) to generate user interface device monitor events. 21 irq1_en. irq1 enable. 1=enable irq1 (keyboard activity) to generate a user interface device monitor event. 20 irq12_en. irq12 enable. 1=enable irq12 (mouse activity) to generate user interface device monitor events. bits description (continued) chapter 4 registers 239 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information general purpose timer pm94 the purpose of this timer is to generate an interrupt at a speci?d time in the future. default: 0000h. attribute: read-write. system inactivity timer register pm98 the system inactivity timer is a counter that may be reloaded by device monitor events as speci?d by pm[8c:50][sit_rld] or by events speci?d by pmac. when it reaches zero, it sets pm20[sit_sts] and may be enabled to generate interrupts. default: 0000 0000h. attribute: see below. bits description 15:13 reserved. 12 gpt_clk. general purpose timer clock source. speci es the clock to the general purpose timer as follows: gpt_clk clock period maximum time (clock times 4096) 0 30.52 microseconds 125 milliseconds 1 32 milliseconds 21.8 minutes 11:0 gpt_cnt. general purpose timer count value. reads provides the current state of the general purpose timer. writes to this eld load a value in the timer. once loaded if either pma4[gpt_en] or pma8[gptsmi_en] is set high the timer counts down to zero and stops. on the clock after gpt_cnt reaches zero, pma0[gpt_sts] is set high. if pma4[gpt_en] and pma8[gptsmi_en] are low, then the general purpose timer does not count and pma0[gpt_sts] cannot be set high. bits description 31:18 reserved. 17:16 clksrc. clock source. read-write. speci es the clock to the system inactivity timer per the following table. clksrc clock period maximum time (clock times 128) 00b 1 millisecond 128 milliseconds 01b 32 milliseconds 4.1 seconds 10b 1 second 128 seconds = 2.13 minutes 11b 64 seconds 136.5 minutes = 2.28 hours 15:8 curcount. read-only. system inactivity timer current count value. 7:0 reload. system inactivity timer reload value. read-write. writes to this eld cause the system inactivity counter to be reloaded with the value written. 240 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information device monitor status register pma0 each of status bits[19:0] is set by a device monitor event (an access to an i/o or memory address range, an irq or a dma request as speci?d by pm[8c:50] or a re-trigger timer time out) and bit[20] is set by the general purpose timer (speci?d by pm94). if any of these events occur, then the status bit is set. if any of these status bits are high and the corresponding enable bit is high (pma4 and pma8), then an interrupt is generated. default: 0000 0000h. attribute: read; set by hardware; write 1 to clear. bits description 31:21 reserved. 20 gpt_sts. general purpose timer status . this bit is set high by the hardware on the clock after pm94[gpt_cnt] reaches zero. however, if pma4[gpt_en] and pma8[gptsmi_en] are both low, then the pma0[gpt_sts] is not set high. 19 pmm2_dm_sts. programmable memory range monitor 2 device monitor status . 18 pmm1_dm_sts. programmable memory range monitor 1 device monitor status . 17 prm4_dm_sts. programmable range monitor 4 device monitor status . 16 prm3_dm_sts. programmable range monitor 3 device monitor status . 15 prm2_dm_sts. programmable range monitor 2 device monitor status . 14 prm1_dm_sts. programmable range monitor 1 device monitor status . 13 tim_dm_sts. timer timeout device monitor status . 12 cardbus1_dm_sts. cardbus1 access device monitor status . 11 cardbus0_dm_sts. cardbus0 access device monitor status . 10 reserved. 9 usrint_dm_sts. user interface device monitor status . 8 aud_dm_sts. audio functions device monitor status . 7 cmb_dm_sts. serial port b (com b) device monitor status . 6 cma_dm_sts. serial port a (com a) device monitor status . 5 lpt_dm_sts. parallel port (lpt) device monitor status . 4 fdd_dm_sts. floppy disk drive device monitor status . 3 dss_dm_sts. ide secondary slave port device monitor status . 2 dsm_dm_sts. ide secondary master port device monitor status . 1 dps_dm_sts. ide primary slave port device monitor status . 0 dpm_dm_sts. ide primary master port device monitor status . chapter 4 registers 241 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information device monitor acpi interrupt enable register pma4 for each of these bits: 1=enable either an sci or an smi interrupt based on the state of pm04[sci_en] if the corresponding status bit in pma0 is set. default: 0000 0000h. attribute: read-write. device monitor smi interrupt enable register pma8 for each of these bits: 1=enable smi interrupt if the corresponding status bit in pma0 is set. default: 0000 0000h. attribute: read-write. bits description 31:21 reserved. 20 gpt_en. general purpose timer acpi interrupt enable . 19 pmm2_dm_en. programmable memory range monitor 2 device monitor acpi interrupt enable . 18 pmm1_dm_en. programmable memory range monitor 1 device monitor acpi interrupt enable . 17 prm4_dm_en. programmable range monitor 4 device monitor acpi interrupt enable . 16 prm3_dm_en. programmable range monitor 3 device monitor acpi interrupt enable . 15 prm2_dm_en. programmable range monitor 2 device monitor acpi interrupt enable . 14 prm1_dm_en. programmable range monitor 1 device monitor acpi interrupt enable . 13 tim_dm_en. timer timeout device monitor acpi interrupt enable . 12 cardbus1_dm_en. cardbus1 access device monitor acpi interrupt enable . 11 cardbus0_dm_en. cardbus0 access device monitor acpi interrupt enable . 10 reserved. 9 usrint_dm_en. user interface device monitor acpi interrupt enable . 8 aud_dm_en. audio functions device monitor acpi interrupt enable . 7 cmb_dm_en. serial port b (com b) device monitor acpi interrupt enable . 6 cma_dm_en. serial port a (com a) device monitor acpi interrupt enable . 5 lpt_dm_en. parallel port (lpt) device monitor acpi interrupt enable . 4 fdd_dm_en. floppy disk drive device monitor acpi interrupt enable . 3 dss_dm_en. ide secondary slave port device monitor acpi interrupt enable . 2 dsm_dm_en. ide secondary master port device monitor acpi interrupt enable . 1 dps_dm_en. ide primary slave port device monitor acpi interrupt enable . 0 dpm_dm_en. ide primary master port device monitor acpi interrupt enable . bits description 31:21 reserved. 20 gptsmi_en. general purpose timer smi enable . 19 pmm2_dmsmi_en. programmable memory range monitor 2 device monitor smi enable . 18 pmm1_dmsmi_en. programmable memory range monitor 1 device monitor smi enable . 17 prm4_dmsmi_en. programmable range monitor 4 device monitor smi enable . 16 prm3_dmsmi_en. programmable range monitor 3 device monitor smi enable . 15 prm2_dmsmi_en. programmable range monitor 2 device monitor smi enable . 14 prm1_dmsmi_en. programmable range monitor 1 device monitor smi enable . 13 tim_dmsmi_en. timer timeout device monitor smi enable . 242 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information irq reload enable for system inactivity timer register pmac each of these bits enable signals to trigger a reload of the system inactivity timer (sit). in the case of the irqrl signals, they only cause the sit to be reloaded whenever they toggle. default: 0000 0000h. attribute: read-write. 12 cardbus1_dmsmi_en. cardbus1 access device monitor smi enable . 11 cardbus0_dmsmi_en. cardbus0 access device monitor smi enable . 10 reserved. 9 usrint_dmsmi_en. user interface device monitor smi enable . 8 aud_dmsmi_en. audio functions device monitor smi enable . 7 cmb_dmsmi_en. serial port b (com b) device monitor smi enable . 6 cma_dmsmi_en. serial port a (com a) device monitor smi enable . 5 lpt_dmsmi_en. parallel port (lpt) device monitor smi enable . 4 fdd_dmsmi_en. floppy disk drive device monitor smi enable . 3 dss_dmsmi_en. ide secondary slave port device monitor smi enable . 2 dsm_dmsmi_en. ide secondary master port device monitor smi enable . 1 dps_dmsmi_en. ide primary slave port device monitor smi enable . 0 dpm_dmsmi_en. ide primary master port device monitor smi enable . bits description 31:20 reserved. 19 bmreqrl. 1=any condition that sets pm00[bm_sts] causes a reload of the system inactivity timer. 18 extsmirl. 1=the status bit associated with the assertion of the extsmi_l pin (pm20[exsmi_sts]) causes a reload of the system inactivity timer. note: as long as the status bit is set, the system inactivity timer is held in its reload value and it does not decrement. 17 initrl. init reload for the system inactivity timer. 1=enables init interrupt to reload the system inactivity timer. 16 nmirl. nmi reload for the system inactivity timer. 1=enables nmi interrupt to reload the system inactivity timer. 0=nmi does affect the system inactivity timer. 15:0 irqrl. irqs reload the system inactivity timer. each of these bits corresponds to an irq (e.g., bit[12] corresponds to irq12). the exception to this is bit[2], which corresponds to the interrupt output of the pic or ioapic (see devb:0x4b[apicen]). for each bit: 1=enable the corresponding irq signal to cause the system inactivity timer to reload whenever it changes state (high to low or low to high). 0=irq signal does affect the system inactivity timer. bits description (continued) chapter 4 registers 243 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information gpio pin interrupt status register (acpi gpe1_sts) pmb0 each of these status bits is driven by the output of the input circuit associated with the gpio pins. bit[0] corresponds to gpio 0; bit[1] corresponds to gpio1, and so forth. the latch associated with each gpio input circuit is cleared when the corresponding bit in this register is written with a 1; writing a 0 has no effect. gpio_sts[25, 24, 23, 22, 18, 14, 3, 2, 1, 0] reside in the vdd_corex power plane and can be used in conjunction with pmb4 as resume events from any sleep state. default: 0000 0000h. attribute: read; set by hardware; write 1 to clear. gpio pin acpi interrupt enable register (acpi gpe1_en) pmb4 for each of these bits: 1=enable either an sci or smi interrupt based on the state of pm04[sci_en] if the corresponding status bit in pmb0 is set. gpio_en[25, 24, 23, 22, 18, 14, 3, 2, 1, 0] reside in the vdd_corex power plane and can be used in conjunction with pmb0 as resume events from any sleep state. default: 0000 0000h. attribute: read-write. gpio pin smi interrupt enable register pmb8 for each of these bits: 1=enable an smi interrupt if the corresponding status bit in pmb0 is set. default: 0000 0000h. attribute: read-write. bits description 31:0 gpio_sts. gpio irq status bits . bits description 31:0 gpio_en. gpio sci/smi enable bits . bits description 31:0 gpio smi enable bits . 244 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information gpio output clock 0 and 1 register pmbc this register speci?s the high time and the low time for the gpio output clocks. these clocks can be selected as the output for any of the gpio pins. these output clocks consist of a 7-bit down counter that is alternately loaded with the high time and the low time. the clock for the counters is selected by clk[1,0]base. default: ffff ffffh. attribute: read-write. general purpose i/o pins gpio[31:0] select registers pm[df:c0] see section 3.7.5 on page 66 for details about the gpio hardware. usage note: to set a gpio pin as a software-controlled output, its corresponding gpio register should be written with the value 04h for a low and the value 05h for a high. default: see the mode ?ld de?ition. attribute: see below. offset: dfh-c0h (one single-byte register for each gpio pin). bits description 31:30 clk1base. see bits[15:14]. 29:23 clk1hi. see bits[13:7]. 22:16 clk1lo. see bits[6:0]. 15:14 clk0base. gpio output clock timer base. speci es the clock for the counter that generates the gpio output clock. 00b=250 microseconds; 01b=2 milliseconds; 10b=16 milliseconds; 11b=128 milliseconds. clk0base speci es the clock for gpio output clock 0 and clk1base speci es the clock for gpio output clock 1. 13:7 clk0hi. gpio output clock high time. speci es the high time for the gpio output clocks in increments of clock speci ed by clk[1,0]base (if the base is 16 milliseconds, then 0 speci es 16 milliseconds, 1 speci es 32 milliseconds, etc.). clk0hi speci es the high time for gpio output clock 0 and clk1hi speci es the high time for gpio output clock 1. 6:0 clk0lo. gpio output clock low time. speci es the low time for the gpio output clocks in increments of the clock speci ed by clk[1,0]base (if the base is 16 milliseconds, then 0 speci es 16 milliseconds, 1 speci es 32 milliseconds, etc.). clk0lo speci es the low time for gpio output clock 0 and clk1lo speci es the low time for gpio output clock 1. bits description 7 reserved. 6 ltch_sts. gpio latch status. read; set by hardware; write 1 to clear. this provides the current state of the latch associated with the input path for the gpio pin that corresponds to the register. chapter 4 registers 245 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information : the table below shows the default states for these registers and the pin de?itions base on the state of mode[1:0]. the ?efault??ld shows the defaults for all the bits in the register. the ?ode?and ?[1:0] ?ld show the value required in order to enable the function speci?d in the ?ignal name column (??speci?s that the bit does not matter). the ?nput path??ld shows how the alternate function signal is mapped into internal logic; ?pio?speci?s that the signal passes through the gpio input path (and can therefore use the polarity, latch and debounce controls from the gpio circuit); ?irect?speci?s that the signal comes directly from the pad; ?/a?speci?s that it is an output signal. 5 rtin. real time in. read-only. this provides the current, not-inverted state of the pad for the gpio pin that corresponds to the register. 4 debounce. debounce the input signal. read-write. 1=the input signal is required to be held active without glitches for 12 to 16 milliseconds before being allowed to set the gpio latch or being capable of being passed along to the circuitry being controlled by the output of the input path. 3:2 mode[1:0]. pin mode select. read-write. these specify the gpio pin mode as follows: mode[1:0] gpio pin mode 00b gpio input 01b gpio output 1xb pin speci ed to as perform alternate function (non-gpio mode). 1:0 x[1:0]. read-write. if the gpio function is not used by the pin (if the pin is programmed as an alternative to the gpio function, e.g., cpusleep_l), then this eld does not matter. if the gpio function is selected, then based on whether the gpio pin is a input or an output (selected by mode also), this register has the meanings shown in the table below. table 59. gpio x[1:0] bit decoding i/o mode bits name function input x0 activehi 0=the pin is active low and the signal is inverted as it is brought into the input path. 1=the pin is active high and therefore not inverted as it is brought through the input path. note: the irq1, irq8, irq12 and pnpirq[2:0] signals that pass through the gpio input path are inverted in the interrupt routing logic before being passed to the pic; therefore, for an active high irqx or pnpirq pin, activehi should be set high for active- low (level triggered) interrupts and low for active-high (edge triggered) interrupts. input x1 latch 0=the latched version of the signal is not selected. 1=the latched version is selected. output x[1:0]=0h output is forced low. output x[1:0]=1h output is forced high. output x[1:0]=2h gpio output clock 0 (speci ed by pmbc[15:0]). output x[1:0]=3h gpio output clock 1 (speci ed by pmbc[31:16]). bits description (continued) 246registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information notes: 1. the signals from gpio[31:28] go directly to the ioapic to drive the interrupt request inputs to some of the redirection-table entries. the polarity of these signals at the ioapic is as seen at the external pins, the polarity is not altered by programming of devb:3x[df:dc]. these signals, from the gpio pins to the ioapic, are not ever disabled, even if the pin s function is other-than gpio. also, see devb:0x4b[mpirq] for details on how gpio[31:28] may be mapped to pirq[a,b,c,d]_l. 2. these pins, corresponding registers, and gpio logic reside on the vdd_iox and vdd_corex power planes, respectively, and are reset by rst_soft. all the other gpio pins reside on the main power supply. 3. when the clkrun_l function is enabled, clkrun_l functionality is automatically enabled. to disable clkrun_l functionally, this pin should be programmed as a gpio. table 60. gpio register default states gpio name control reg signal name default mode input path notes gpio0 pmc0 acav 08h (acav input) 1xb gpio 2 gpio1 pmc1 agpstop_l 05h (gpio1 output, high) 1xb n/a 2 gpio2 pmc2 batlow_l 08h (batlow_l input) 1xb gpio 2 gpio3 pmc3 c32khz 08h (c32khz output) 1xb n/a 2 gpio4 pmc4 gpio4 04h (gpio4 output, low) 1xb n/a 4 gpio5 pmc5 clkrun_l 04h (gpio5 output, low) 1xb direct 3 gpio6 pmc6 cpusleep_l 05h (gpio6 output, high) 1xb n/a gpio7 pmc7 cpustop_l 05h (gpio7 output, high) 1xb n/a gpio8 pmc8 gpio8 05h (gpio8 output, high) 1xb n/a gpio9 pmc9 fancon1 08h (fancon1 output) 1xb n/a gpio10 pmca fanrpm 08h (fanrpm input) 1xb direct gpio11 pmcb intirq8_l 05h (gpio11 output, high) 1xb n/a gpio12 pmcc irq1 09h (irq1 input) 1xb gpio gpio13 pmcd irq6 09h (irq6 input) 1xb gpio gpio14 pmce gpio14 00h (gpio14 input) 0xb n/a 2 gpio15 pmcf irq12 09h (irq12 input) 1xb gpio gpio16 pmd0 gpio16 00h (gpio 16 input) 0xb n/a gpio17 pmd1 gpio17 00h (gpio 17 input) 0xb n/a gpio18 pmd2 lid 00h (gpio 18 input) 1xb direct 2 gpio19 pmd3 pnpirq0 09h (pnpirq0 input) 1xb gpio gpio20 pmd4 pnpirq1 09h (pnpirq1 input) 1xb gpio gpio21 pmd5 pnpirq2 09h (pnpirq2 input) 1xb gpio gpio22 pmd6 smbalert0_l 08h (smbalert0_l input) 1xb direct 2 gpio23 pmd7 slpbtn_l 08h (slpbtn_l input) 1xb gpio 2 gpio24 pmd8 smbalert1_l 08h (smbalert1_l input) 1xb direct 2 gpio25 pmd9 suspend_l 08h (suspend_l output) 1xb n/a 2 gpio26 pmda gpio26 00h (gpio 26 input) 0xb n/a gpio27 pmdb gpio27 00h (gpio 27 input) 0xb n/a gpio28 pmdc gpio28 00h (gpio28 input) 0xb n/a 1 gpio29 pmdd gpio29 00h (gpio29 input) 0xb n/a 1 gpio30 pmde gpio30 00h (gpio30 input) 0xb n/a 1 gpio31 pmdf gpio31 00h (gpio31 input) 0xb n/a 1 chapter 4 registers 247 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 4. when programmed for alternate function, the status of wdt00[wfir] can be observed externally. smbus global status register pme0 default: 0000h. attribute: read; set by hardware; write 1 to clear. bits description 15:12 reserved. 11 smb_bsy. smbus busy. read-only. 1=the smbus is currently busy with a cycle generated by either the host or another smbus master. 10 smba_sts. smbalert_l interrupt status. this bit is set high by the hardware when smbalert_l is asserted low. this bit is not set unless the smbalert_l function is selected by pmd6. this bit may trigger an smi or sci interrupt if enabled to do so by pme2[smba_en]. 9 hslv_sts. host-as-slave address match status. this bit is set high by the hardware when an smbus master (including the host controller) generates an smbus write cycle with a 7-bit address that matches the one speci ed by pmee. this bit is not set until the end of the acknowledge bit after the last byte is transferred; however, if a time out occurs after the address match occurs and before last acknowledge, then this bit is not set. this may trigger an smi or sci interrupt if enabled to do so by pme2[hslv_en]. this bit resides on the vdd_corex power plane. 8 snp_sts. snoop address match status. this bit is set high by the hardware when an smbus master (including the host controller) generates an smbus cycle with a 7-bit address that matches the one speci ed by pmef. this bit is not set until the end of the acknowledge bit after the last byte is transferred; however, if a time out occurs after the address match occurs and before the last acknowledge, then this bit is not set. this bit may trigger an smi or sci interrupt if enabled to do so by pme2[snp_en]. this bit resides on the vdd_corex power plane. 7:6 reserved. 5 to_sts. time out error status. this bit is set high by the hardware when a slave device forces a time out by holding the smbusc pin low for more than 25 milliseconds. this bit may trigger an smi or sci interrupt if enabled to do so by pme2[hcyc_en]. 4 hcyc_sts. host cycle complete status. this bit is set high by the hardware when a host cycle completes successfully. this bit may trigger an smi or sci interrupt if enabled to do so by pme2[hcyc_en]. note: it is illegal for sw to attempt to clear this bit when it is not yet set. 3 hst_bsy. host controller busy. read-only. 1=the smbus host controller is busy with a cycle. 2 prerr_sts. protocol error status. this bit is set high by the hardware when a slave device does not generate an acknowledge at the appropriate time during a host smbus cycle. this bit may trigger an smi or sci interrupt if enabled to do so by pme2[hcyc_en]. 1 col_sts. host collision status. this bit is set high by the hardware when a host transfer is initiated while the smbus is busy. this bit may trigger an smi or sci interrupt if enabled to do so by pme2[hcyc_en]. note: if the smbus is detected busy prior to the command to initiate a host transfer, then the ic waits for the initial transaction to complete before executing the host transfer and this bit is not set; this bit may only be set when host transactions start at approximately the same time as other transactions. 0 abrt_sts. host transfer abort status. this bit is set high by the hardware after a host transfer is aborted by pme2[abort] command. this bit may trigger an smi or sci interrupt if enabled to do so by pme2[hcyc_en]. 248 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information smbus global control register pme2 most of these bits enable either an sci or an smi interrupt based on the state of pm04[sci_en] if the corresponding status bit is set. default: 0000h. attribute: read-write. bits description 15:11 reserved. 10 smba_en. smbalert_l interrupt enable. 1=enables an smi or sci interrupt when pme0[smba_sts] is set high. this bit has no effect unless the smbalert_l function is selected by pmd6. 9 hslv_en. host-as-slave address match interrupt enable. 1=enables an smi or sci interrupt when pme0[hslv_sts] is set high. this bit resides on the vdd_corex power plane. 8 snp_en. snoop address match interrupt enable. 1=enables an smi or sci interrupt when pme0[snp_sts] is set high. this bit resides on the vdd_corex power plane. 7:6 reserved. 5 abort. abort current host transfer command. write-only. 1=the smbus logic generates a stop event on the smbus pins as soon as possible (there may be a delay if the smbus slave is generating zeros during a read cycle). after the stop event is generated, pme0[abrt_sts] is set high. 4 hcyc_en. host smbus controller interrupt enable. 1=the smbus host controller status bits, pme0[to_sts, hcyc_sts, prerr_sts, col_sts, abrt_sts], are enabled to generate smi or sci interrupts. 3 hostst. host start command. write-only. 1=the smbus host logic initiates the smbus cycle speci ed by cyctype. writes to this eld are ignored while pme0[hst_bsy] is active. 2:0 cyctype. host-generated smbus cycle type . writes to this eld are ignored while pme0[hst_bsy] is active. this eld speci es the type of smbus cycle that is generated when it is initiated by the hostst command. here is how it is decoded (for each of the registers, the slave address is speci ed by pme4[7:1] and receive or read versus send or write is speci ed by pme4[0]): cyctype smbus cycle type registers 000b quick command data bit in pme4[0] 001b receive or send byte data in pme6[7:0]. if the address in pme4 is 0001_1001b and data received is 111_0xxxb, then another byte is received in pme6[15:8]; see also the smbalert description in section 3.7.3 on page 65. 010b read or write byte command in pme8; data in pme6[7:0] 011b read or write word command in pme8; data in pme6[15:0] 100b process call command in pme8; write data is placed in pme6[15:0]; then this data is replaced with the read data in the second half of the command 101b read or write block command in pme8; count data in pme6[5:0]; block data in the pme9 fifo 11xb reserved chapter 4 registers 249 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information smbus host address register pme4 default: 0000h. attribute: read-write. smbus host data register pme6 default: 0000h. attribute: read-write. smbus host command field register pme8 default: 00h. attribute: read-write. smbus host block data fifo access port pme9 default: 00h. attribute: see below. bits description 15:8 hst10ba. host 10-bit address lsbs. this eld stores the second byte of the address, used in 10- bit smbus host-as-master transfers. if hstaddr == 1111_0xxb, then the cycle is speci ed to use 10-bit addressing. if hstaddr is any other value, then hst10ba is not utilized. 7:1 hstaddr. host cycle address. this speci es the 7-bit address to the smbus generated by the host (as a master) during smbus cycles that are initiated by pme2[hostst]. 0 readcyc. host read (high) write (low) cycle. 1=speci es that the cycle generated by a write to pme2[hostst] is a read or receive command. 0=cycle is a write or send command. bits description 15:0 hstdata. host cycle data. this register is written to by software to specify the data to be passed to the smbus during write and send cycles. it is read by software to specify the data passed to host controller by the smbus during read and receive cycles. bit[0] speci es the data written or read during the quick command cycle. bits[7:0] specify the data for byte read and write cycles, send byte cycles, and receive byte cycles. bits[15:0] are used for word read and write cycles and process calls. bits[5:0] are used to specify the count for block read and write cycles. bits description 7:0 hstcmd. host cycle command. this speci es the command eld passed to the smbus by the host controller during read byte, write byte, read word, write word, process call, block read, and block write cycles. host cycles are initiated by pme2[hostst]. bits description 7:0 hstfifo. host block read-write fifo. for block write commands, software loads 1 to 32 bytes into this port before sending them to the smbus through the pme2[hostst] command. for block read commands, software reads 1 to 32 bytes from this port after the block read cycle is complete. if, during a block read or write, an error occurs, then the fifo is ushed by the hardware. read and write accesses to this port while the host is busy (pme0[hst_bsy]) are ignored. 250 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information smbus host-as-slave data register pmea default: 0000h. attribute: read-only. smbus host-as-slave device address register pmec this register resides on the vdd_corex power plane. default: 0000h. attribute: read-only. smbus host-as-slave host address register pmee this register resides on the vdd_corex power plane. default: 10h. attribute: read-write. bits description 15:0 hslvdata. host-as-slave data. when the logic detects that the current smbus cycle is directed to the host s slave logic (because the address matches pmee), then the data transmitted to the ic during the cycle is latched in this register. also, if the address matches the snoop address in pmef, then the cycle type is assumed to be a write word and the data is stored in this register. this register resides on the vdd_corex power plane. bits description 15:8 hslv10da. host-as-slave 10-bit device address lsbs. this eld stores the second byte of the device address used in 10-bit smbus transfers to the host as a slave. if hslvda == 1111_0xxb, then the cycle is speci ed by the smbus speci cation to transmit a 10-bit device address to the host-as- slave logic and the second byte of that device address is stored in this eld. if hslvda is any other value, then hslv10ba is not utilized. 7:1 hslvda. host-as-slave device address. when the logic detects that the current smbus cycle is directed to the host s slave logic (because the address matches pmee), then the device address transmitted to the ic during the command phase of the cycle is latched in this register. also, if the smbus address matches the snoop address in pmef, then the cycle type is assumed to be a write word and bits[7:1] of the command eld for the cycle are placed in this eld. 0 snplsb. snoop command lsb. if the smbus cycle address matches pmef, then the cycle type is assumed to be a write word. the lsb of the command eld for the cycle is placed in this bit (and the other 7 bits are placed in hslvda). bits description 7:1 hslvaddr. host-as-slave address. the ic compares the address generated by masters over the smbus to this eld to determine if there is a match (also, for a match to occur, the read-write bit is required to specify a write command). if a match occurs, then the cycle is assumed to be a write word command to the host, with the slave s device address transmitted during the normal command phase. the device address is captured in pmec and the data is capture in pmea for the cycle. after the cycle is complete, pme0[hslv_sts] is set. 0 reserved. chapter 4 registers 251 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information smbus snoop address register pmef this register resides on the vdd_corex power plane. default: 10h. attribute: read-write. random number register pmf0 pmf0 and pmf4 together support of the random number generator (rng) function. when pmf4[rngdone] is 1, then the value in pmf0 has been updated. reading pmf0 clears rngdone until the next valid random number is available in pmf0. new random numbers are generated approximately 128 microseconds after pmf0 is read. if pmf0 is read while rngdone = 0, then the value returned is all zeros. default: not deterministic. attribute: read-only. random number status register pmf4 default: 0000 0001h (see note in bit 0). attribute: read-only. bits description 7:1 snpaddr. snoop address. the ic compares the address generated by masters over the smbus to this eld to determine if there is a match (regardless as to whether it is a read or a write). if there is a match, then pme0[snp_sts] is set high after the cycle completes. if the address speci ed here matches pmee, then pme0[snp_sts] is not set high. 0 reserved. bits description 31:0 random_num. random number . bits description 31:1 reserved. 0 rngdone. random number generator number generation process complete . see pmf0. note: this bit is low after the trailing edge of reset_l and only goes high after the rst random number is valid in pmf0, less than 500 microseconds later. 252 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information fan control register pmf8 this register speci?s the frequency and duty cycle for the fancon[1:0] signals. the fancon signals are clocks with a period speci?d by fc[1:0]fq and a duty cycle speci?d by fc[1:0]hi. bits[7:0] specify fancon0 and bits[15:8] specify fancon1. the system sleep state and these con?uration bits interact to specify the fancon[1:0] signal behavior as follows: if ((system state=pos) & (fcxpos=1)) then fanconx=0; else if((fcxtherm=1) & (therm_l=0)) then fanconx=1; else fanconx is controlled by the fcxfq and fcxhi fields; default: 0f0fh. attribute: read-write. bits description 15 reserved. 14 fc1pos. see bit 6. 13 fc1therm. see bit 5. 12 fc1fq. see bit 4. 11:8 fc1hi. see bits[3:0]. 7 reserved. 6 fc0pos. fancon0 power-on-suspend control. 1=when the system is placed into the pos state, fancon0 goes low. 0=the system sleep state has no affect on fancon0. 5 fc0therm. fancon0 therm_l control. 1=if the therm_l pin is asserted then fancon0 goes high. 0=therm_l has no affect on fancon0. this bit is ignored if the system is in pos and fc0pos is high. 4 fc0fq. fancon0 frequency. the frequency of fancon[1:0] is speci ed by this bit. 0=a fancon[1:0] period of 15 milliseconds. 1=a fancon[1:0] period of 240 milliseconds. 3:0 fc0hi. fancon0 high time. speci es the percentage of time that fancon[1:0] is high as: percent high time = fc[1:0]hi/15; (the rest of the time of the clock period, fancon[1:0] is low). e.g., if fc1hi == 0, then the fancon1 is low all the time; if fc1hi == 1, then fancon1 is high 1/15 th of the time; if fc1hi == 15, then fancon1 is high all the time. chapter 4 registers 253 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 4.8 ac 97 controller registers 4.8.1 ac 97 audio register 4.8.1.1 ac 97 audio con guration registers (devb:5xxx) ac 97 audio controller vendor and device id devb:5x00 default: 746d_1022h attribute: read-write once ac 97 audio controller command and status devb:5x04 default: 0200_0000h attribute: see below. ac 97 audio controller revision id and class code devb:5x08 default: 0401_00xxh see below. attribute: read-only bits description 31:16 ac97id. provides the ac 97 device identi cation . 15:0 amdid. provides amd s pci vendor identi cation . bits description 31:16 stat. read-only. 15:0 cmd. cmd[15:3]: read-only. cmd[2]: bmen . bus master enable . read-write. 1=enables bus master capability (scatter/gather). 0=scatter/gather operation is disabled. cmd[1]: read-only. cmd[0]: ioen . i/o space . read-write. 1=enables access to the i/o space for this device, the mixer registers and the bus master controller registers. 0=accesses to these registers are disabled. bits description 31:24 baseclass. these bits are xed at 04h indicating a multimedia device. 23:16 subclass. these bits are xed at 01h indicating an audio device. 15:8 progif. 7:0 revid. ac '97 audio controller silicon revision . the value of this register is revision-dependent. 254 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information ac 97 audio controller bist, header and latency devb:5x0c default: 0000_0000h attribute: see below. ac 97 audio mixer base address devb:5x10 default: 0000_0001h attribute: see below. ac 97 audio controller bus master base address devb:5x14 default: 0000_0001h attribute: see below. bits description 31:24 bist. read-only. 23:16 header. read-only. 15:8 latency. read-write. the latency timer de nes the minimum amount of time, in pci clock cycles, that the bus master can retain ownership of the bus. 7:0 read-only. bits description 31:8 amba. base address . read-write. these bits are used in the i/o space decode of the audio interface registers. there is a maximum i/o block size of 256 bytes for this base address 7:1 read-only. 0 rte. resource type indicator . this bit is xed to 1, indicating a request for i/o space. bits description 31:6 abmba. base address . read-write.these bits are used in the i/o space decode of the audio pci bus master controller registers. there is a maximum i/o block size of 64 bytes for this base address. 5:1 read-only. 0 rte. resource type indicator . this bit is xed to 1, indicating a request for i/o space. chapter 4 registers 255 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information ac 97 audio controller subsystem and subsystem vendor id devb:5x2c default: 0000_0000h attribute: read-write once ac 97 audio controller interrupt line and interrupt pin devb:5x3c default: 0200h attribute: see below. ac 97 audio controller pcm out descriptor shadow devb:5x40 default: 0000_0000h attribute: read-only ac 97 audio controller pcm in descriptor shadow devb:5x44 default: 0000_0000h attribute: read-only bits description 31:16 subsysid. this register should be implemented for any function that could be instantiated more than once in a given system. for example, a system with 2 audio subsystems, one down on the motherboard and the other plugged into a pci expansion slot, should have this register implemented. this register, in combination with the subsystem vendor id register, enables the operating environment to distinguish one audio subsystem from the other(s). 15:0 subvenid. this register should be implemented for any function that could be instantiated more than once in a given system. for example a system with 2 audio subsystems, one down on the motherboard and the other plugged into a pci expansion slot, should have this register implemented. this register, in combination with the subsystem id register, enables the operating environment to distinguish one audio subsystem from the other(s). bits description 15:11 read-only. 10:8 intpin. read-only. indicates which pci interrupt pin is used for the ac '97 audio interrupt. hardwired to 010b to select pirqb_l. 7:0 intline. read-write. this data is not used by hardware. it is used to communicate across software the interrupt line that the interrupt pin is connected to. bits description 31:1 descr. descriptor current value . this is a test register for reading the current descriptor value. 0 read-only. bits description 31:1 descr. descriptor current value . this is a test register for reading the current descriptor value. 0 read-only. 256registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information ac 97 audio controller microphone in descriptor shadow devb:5x48 default: 0000_0000h attribute: read-only ac 97 audio controller general control devb:5x4c default: 00h attribute: see below 4.8.1.2 ac '97 audio mixer registers the audio mixer registers are physically located in the codec. accesses to these registers are forwarded through the ac link to the codec. writes to a codec are completed when the data are inserted in the output slot. reads from a codec may cause a pci retry cycle. for more information about these registers see the ac '97 spec. table 61 on page 256 shows the register address space for the audio mixer registers. these registers are exposed in i/o space. the base address register for these registers is devb:5x10. bits description 31:1 descr. descriptor current value . this is a test register for reading the current descriptor value. 0 read-only. bits description 7:3 reserved 2 swlsb. subwoofer is lsb .read-write. when cleared to 0b the center front channel sample is always placed in the least signi cant sample of the subwoofer/center front information pair, i.e., the audio data stream as represented in the host memory buffer pages must start with a center front channel sample. when set to 1b the subwoofer channel sample is always placed in the least signi cant sample of the center front/subwoofer information pair, i.e., the audio data stream as represented in the host memory buffer pages must start with a subwoofer channel sample. 1 rrlsb. right rear is lsb . read-write. when cleared to 0b the left rear channel sample is always placed in the least signi cant sample of the right rear/left rear information pair, i.e., the audio data stream as represented in the host memory buffer pages must start with a left rear channel sample. when set to 1b the right rear channel sample is always placed in the least signi cant sample of the right rear/left rear information pair, i.e., the audio data stream as represented in the host memory buffer pages must start with a right rear channel sample. 0 rflsb. right front is lsb . read-write. when cleared to 0b the left channel sample is always placed in the least signi cant sample of the stereo information pair, i.e., the stereo audio data stream as represented in the host memory buffer pages must start with a left channel sample. when set to 1b the right channel sample is always placed in the least signi cant sample of the stereo information pair, i.e., the stereo audio data stream as represented in the host memory buffer pages must start with a right channel sample. table 61. audio mixer register address audio mixer registers primary secondary 1 chapter 4 registers 257 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 4.8.1.3 ac 97 audio controller bus master registers these registers are located in i/o space and reside in the ac '97 controller. the three channels, pcm out, pcm in, and microphone in, each have their own set of bus mastering registers. the following register descriptions apply to all three channels. the base address register for these registers is devb:5x14. see section 4.1.2 on page 136 for a description of the register naming convention. 00h 80h reset 02h 82h master volume mute 04h 84h headphone volume mute 06h 86h master volume mono mute 08h 88h master tone (r & l) 0ah 8ah pc_beep volume mute 0ch 8ch phone volume mute 0eh 8eh mic volume mute 10h 90h line in volume mute 12h 92h cd volume mute 14h 94h video volume mute 16h 96h aux volume mute 18h 98h pcm out volume mute 1ah 9ah record select 1ch 9ch record gain mute 1eh 9eh record gain mic mute 20h a0h general purpose 22h a2h 3d control 24h a4h ac 97 reserved 26h a6h powerdown ctrl/stat 28h a8h extended audio 2ah aah extended audio ctrl/stat 2ch ach pcm front dac rate 2eh aeh pcm surround dac rate 30h b0h pcm lfe dac rate 32h b2h pcm lr adc rate 34h b4h mic adc rate 36h b6h 6ch vol: c, lfe mute 38h b8h 6ch vol: l, r surround mute 3ah:56h bah:d6h reserved 58h d8h vendor reserved 2 7ah fah vendor reserved 2 7ch fch vendor id1 2 7eh feh vendor id2 2 notes: 1. the ic does not support audio as a secondary codec. 2. registers 58h, 7ah, 7ch, 7eh, d8h, fah, fch, and feh are multiplexed between audio and modem functions. table 61. audio mixer register 258 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information the global control (ac2c), global status (ac30), and codec access semaphore (ac34) registers are aliased to the same global registers in the audio and modem i/o space. therefore, a read-write to these registers in either audio or modem i/o space affects the same physical register. the following status and con?uration bits are powered by the aux plane: ac30[md3] ac30[ad3] ac 97 audio controller buffer descriptor list base address ac00, ac10, ac20 default: 0000_0000h attribute: see below. table 62. audio controller bus master registers mnemonic name default ac00 pcm in buffer descriptor list base address 0000_0000h ac04 pcm in current index value 00h ac05 pcm in last valid index 00h ac06 pcm in status 0001h ac08 pcm in position in current buffer 0000h ac0a pcm in prefetched index value 00h ac0b pcm in control 00h ac10 pcm out buffer descriptor list base address 0000_0000h ac14 pcm out current index value 00h ac15 pcm out last valid 00h ac16 pcm out status 0001h ac18 pcm out position in current buffer 0000h ac1a pcm out prefetched index 00h ac1b pcm out control 00h ac20 mic. in buffer descriptor list base address 0000_0000h ac24 mic. in current index value 00h ac25 mic. in last valid 00h ac26 mic. in status 0001h ac28 mic. in position in current buffer 0000h ac2a mic. in prefetched index 00h ac2b mic. in control 00h ac2c global control 0000_0000h ac30 global status 0030_0000h ac34 codec access semaphore 00h bits description 31:3 bdlba. buffer descriptor list base address . read-write. the entries should be aligned on 8 byte boundaries. 2:0 0h chapter 4 registers 259 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information ac 97 audio controller current index value ac04, ac14, ac24 default: 00h attribute: see below. ac 97 audio controller last valid index ac05, ac15, ac25 default: 00h attribute: see below. ac 97 audio controller status ac06, ac16, ac26 default: 0001h attribute: see below. bits description 7:5 0h 4:0 civ. current index value . read-only. these bits represent which buffer descriptor within the list of 32 descriptors is being processed currently. as each descriptor is processed, this value is incremented. bits description 7:5 0h 4:0 lvi. read-write. these bits indicate the last valid descriptor in the list. this value is updated by the software as it prepares new buffers and adds to the list. bits description 15:5 reserved. 4 fifoerr. fifo error . read-write. the hardware sets this bit if an under-run or over-run occurs. this bit is cleared by writing a 1 to this bit position. 3 bcis. buffer completion interrupt status . read-write. this bit is set by the hardware after the last sample of a buffer has been processed, and if the interrupt on completion (ioc) bit is set in the command byte of the buffer descriptor. remains active until software clears bit. this bit is cleared by writing a 1 to this bit position. 2 lvbci. last valid buffer completion interrupt . read-write.this bit is set to 1 by hardware when last valid buffer has been processed. it remains active until cleared by software. this bit indicates the occurrence of the event signi ed by the last valid buffer being processed. thus, this is an event status bit that can be cleared by software once this event has been recognized. this event causes an interrupt if the enable bit in the control register is set. this bit is cleared by writing a 1 to this bit position. 1 celv. current equals last valid . read-only.1 = current index is equal to the value in the last valid index register, and the buffer pointed to by the civ has been processed (i.e., after the last valid buffer has been processed). this bit is very similar to bit 2, except this bit re ects the state rather than the event. this bit re ects the state of the controller, and remains set until the controller exits this state. hardware clears this bit when controller exits state (i.e., until a new value is written to the lvi register). 0 bmch. bus master controller halted . read-only. this bit is set to 1b because of the run/pause bit being cleared in which case bmch may or may not be asserted immediately, depending on whether a pci transaction had previously been requested. if a pci transaction had previously been requested, bmch assertion occurs after completion of the single transaction. bus master controller halted can also happen once the controller has processed the last valid buffer in which case it sets acx6[celv] and halts. this bit is cleared and the bus master controller resumes operation when both the run/ pause bit is set and the controller has exited the acx6[celv] status. 260 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information notes: 1. modem in: fifo error indicates a fifo overrun. the fifo pointers don't increment, the incoming data is not written into the fifo, thus is lost. 2. modem out: fifo error indicates a fifo under-run. the sample transmitted in this case should be the last valid sample. ac 97 audio controller position in current buffer ac08, ac18, ac28 default: 0000h attribute: read-only. ac 97 audio controller prefetched index value ac0a, ac1a, ac2a default: 00h attribute: read-only. ac 97 audio controller control register ac0b, ac1b, ac2bg default: 00h attribute: see below. bits description 15:0 picb. position in current buffer . these bits represent the number of samples left to be processed in the current buffer. bits description 7:5 0h 4:0 piv. these bits represent which buffer descriptor in the list has been prefetched. bits description 7:5 reserved 4 iocen. interrupt on completion enable . read-write. ithis bit controls whether or not an interrupt occurs when a buffer completes with the ioc bit set in its descriptor. 1 = enable. 0 = disable; bit 3 in the status register is still set, but the interrupt does not occur. chapter 4 registers 261 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information ac 97 audio controller global control ac2c default: 0000_0000h attribute: see below. 3 feien. fifo error interrupt enable .read-write. this bit controls whether the occurrence of a fifo error causes an interrupt or not. 1 = enable. 0 = disable; bit 4 in the status register is set, but the interrupt does not occur. 2 lvbien. last valid buffer interrupt enable . read-write. this bit controls whether the completion of the last valid buffer causes an interrupt or not. 1 = enable. 0 = disable; bit 2 in the status register is still set, but the interrupt does not occur. 1 regrst. register reset . read-write. 1 = contents of all registers of the bus master engine including the fifos are reset, except the interrupt enable bits (bits 4,3,2 of this register). software needs to set this bit. it must be set only when the run/pause bit runbm is cleared and acx6[bmch] is asserted. setting it when either runbm is asserted (set) or when acx6[bmch] is de-asserted (clear) causes unde ned consequences. this bit is self-clearing (software need not clear it). 0 = removes reset condition. 0 runbm. run/pause bus master . read-write. 1 = enable bus master operation. 0 = disable bus master; this results in all state information being retained (i.e., master mode operation can be stopped and then resumed). bits description 31:22 reserved 21:20 pcm46en. pcm 4/6 enable . read-write.con gures pcm output for 2, 4 or 6 channel mode 00 = 2-channel mode (default) 01 = 4 channel mode 10 = 6 channel mode 11 = reserved 19:6 reserved 5 srien. secondary resume interrupt enable . read-write. 1 = enable an interrupt to occur when the secondary codec causes a resume event on the ac-link. 0 = disable interrupt. 4 prien. primary resume interrupt enable . read-write. 1 = enable an interrupt to occur when the primary codec causes a resume event on the ac-link. 0 = disable interrupt. 262 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information ac 97 audio controller global status ac30 default: 0030_0000h attribute: see below. 3 shutoff. aclink shut off . read-write. 1 = disable the ac-link signals (drive all ac 97 outputs low and ignore all ac 97 input buffer enables). 0 = enable the ac-link signals. wake-up event detection is independent of this bit. 2 wrst. ac 97 warm reset .read-write. writing a 1 to this bit causes a warm reset to occur on the ac-link. the warm reset awakens a suspended codec without clearing its internal registers. if software attempts to perform a warm reset while acclk is running, the write is ignored and the bit is not changed. a warm reset can only occur in the absence of acclk. this bit is self-clearing (it clears itself after the reset has occurred and acclk has started). 1 crst_l. ac 97 cold reset, active low . read-write. writing a 0 to this bit causes a cold reset to occur on the ac-link. all data in the codec is lost. software needs to set this bit no sooner than after 1 s has elapsed. this bit re ects the state of the acrst_l pin. this bit is cleared to 0 upon entering s3/s4/s5 sleep states, and by sm_reset_l and reset_l assertions. 0 gpiien. gpi interrupt enable . read-write. this bit controls whether the change in status of any gpi (general purpose input/output, con gured as an input) causes an interrupt. 1 = the change on value of a gpi causes an interrupt and sets bit 0 of the global status register. 0 = bit 0 of the global status register is set, but an interrupt is not generated. bits description 31:22 reserved 21 pcm6cap. 6 channel capability . read-only. hardwired to 1. 0 = ac 97 doesn t support 6-channel audio output. 1 = ac 97 supports 6-channel audio output. 20 pcm4cap. 4 channel capability . read-only. hardwired to 1. 0 = ac 97 doesn t support 4-channel audio output. 1 = ac 97 supports 4-channel audio output. 19:18 reserved 17 md3. power down semaphore for modem . read-write. this bit is used by software in conjunction with the ad3 bit to coordinate the entry of the two codecs into d3 state. this bit resides in the vdd_corex well and maintains context across power states. this bit has no hardware function. 16 ad3. power down semaphore for audio . read-write. this bit is used by software in conjunction with the md3 bit to coordinate the entry of the two codecs into d3 state. this bit resides in the vdd_corex well and maintains context across power states. this bit has no hardware function. 15 rcstat. read complete status . read-write. this bit indicates the status of codec read completions. 1 = codec read failed due to one of the following errors: a time-out, or that acclk is detected to not be operating adequately. this bit remains set until being cleared by software. 0 = codec read completes normally. this bit is cleared by writing a 1 to this bit position. 14 s12bit3. bit 3 of slot 12 . display bit 3 of the most recent slot 12 from modem codec. 13 s12bit2. bit 2 of slot 12 . display bit 2 of the most recent slot 12 from modem codec. bits description chapter 4 registers 263 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 12 s12bit1. bit 1 of slot 12 . display bit 1 of the most recent slot 12 from modem codec. 11 srint. secondary resume interrupt . read-write. this bit indicates that a resume event occurred on acsdi[1]. 1 = resume event occurred. cleared by writing a 1 to this bit position. 10 print. primary resume interrupt . read-write. this bit indicates that a resume event occurred on acsdi[0]. 1 = resume event occurred. cleared by writing a 1 to this bit position. 9 scrdy. secondary codec ready . read-only. re ects the state of the codec ready bit in acsdi[1]. bus masters ignore the condition of the codec ready bits. software must check this bit before starting the bus masters. this bit is cleared with assertion of glob_cnt[shutoff]. this bit is also cleared when acclk is detected to not be operating adequately. 8 pcrdy. primary codec ready . read-only. re ects the state of the codec ready bit in acsdi[0]. bus masters ignore the condition of the codec ready bits. software must check this bit before starting the bus masters. this bit is cleared with assertion of ac2c[shutoff]. this bit is also cleared when acclk is detected to not be operating adequately. 7 micint. mic in interrupt . read-only. this bit indicates that one of the mic in channel interrupts occurred. 1 = interrupt occurred. when the speci c interrupt is cleared, this bit is cleared automatically. 6 point. pcm out interrupt . read-only. this bit indicates that one of the pcm out channel interrupts occurred. 1 = interrupt occurred. when the speci c interrupt is cleared, this bit is cleared automatically. 5 piint. pcm in interrupt . read-only. this bit indicates that one of the pcm in channel interrupts occurred. 1 = interrupt occurred. when the speci c interrupt is cleared, this bit is cleared automatically. 4 reserved 3 reserved 2 moint. modem out interrupt . read-only. this bit indicates that one of the modem out channel interrupts occurred. 1 = interrupt occurred. when the speci c interrupt is cleared, this bit is cleared automatically. 1 miint. modem in interrupt . read-only. this bit indicates that one of the modem in channel interrupts occurred. 1 = interrupt occurred. when the speci c interrupt is cleared, this bit is cleared automatically. 0 gpiint. gpi status change interrupt . read-write. this bit is set whenever bit 0 of slot 12 is set. this happens when the value of any of the gpios currently de ned as inputs changes. if 1 this bit sets also pm20[ac97_sts]. 1 = input changed. this bit is cleared by writing a 1 to this bit position. bits description (continued) 264 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information ac 97 audio controller codec access semaphore ac34 default: 00h attribute: see below. 4.8.2 ac '97 modem registers 4.8.2.1 ac '97 modem con guration registers (devb:6xxx) ac 97 modem controller vendor and device id devb:6x00 default: 746e_1022h attribute: read-write once. ac 97 modem controller command and status devb:6x04 default: 0200_0000h attribute: see below. bits description 7:1 reserved 0 cas. codec access semaphore . read-write. this bit is read by software to check whether a codec access is currently in progress. the act of reading this register sets this bit to 1. the driver that reads this bit can then perform a codec i/o access. once the access is completed, or if acclk is detected to not be operating adequately, hardware automatically clears this bit. 0 = no access in progress. if and only if cas = 1 and a codec access has not yet been requested (i.e., the pci transaction has not yet been initiated), cas may be cleared by writing a 0 to this bit position. bits description 31:16 ac97id. provides the ac 97 device identi cation . 15:0 amdid. provides amd s pci vendor identi cation . bits description 31:16 stat. read-only. 15:0 cmd. cmd[15:3]: read-only. cmd[2]: bmen . bus master enable . read-write. 1 = enables bus master capability (scatter/gather). 0 = scatter/gather operation is disabled. cmd[1]: memory space . read-only. cmd[0]: ioen . i /o space . read-write. 1 = enables access to the i/o space for this device, the mixer registers and the bus master controller registers. 0 = accesses to these registers are disabled. chapter 4 registers 265 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information ac 97 modem controller revision id and class code devb:6x08 default: 0703_00xxh see below. attribute: read-only. ac 97 modem controller bist, header and latency devb:6x0c default: 0000_0000h attribute: see below. ac 97 modem mixer base address devb:6x10 default: 0000_0001h attribute: see below. ac 97 modem controller bus master base address devb:6x14 default: 0000_0001h attribute: see below. bits description 31:24 baseclass. these bits are xed at 07h indicating a simple communications controller. 23:16 subclass. these bits are xed at 03h indicating a generic modem. 15:8 progif. 7:0 revid. ac '97 modem controller silicon revision . the value of this register is revision-dependent. bits description 31:24 bist. read-only. 23:16 header. read-only. 15:8 latency. read-write. the latency timer de nes the minimum amount of time, in pci clock cycles, that the bus master can retain ownership of the bus. 7:0 read-only. bits description 31:8 mmba. base address . read-write. these bits are used in the i/o space decode of the modem interface registers. there is a maximum i/o block size of 256 bytes for this base address 7:1 read-only. 0 rte. resource type indicator . this bit is set to one, indicating a request for i/o space. bits description 31:7 mbmba. base address . read-write. these bits are used in the i/o space decode of the modem pci bus master controller registers. there is a maximum i/o block size of 128 bytes for this base address. 6:1 read-only. 0 rte. resource type indicator . this bit is set to one, indicating a request for i/o space. 266 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information ac 97 modem controller subsystem and subsystem vendor id devb:6x2c default: 0000_0000h attribute: read-write once. ac 97 modem controller interrupt line and interrupt pin devb:6x3c default: 0200h attribute: see below. ac 97 modem controller modem out descriptor shadow devb:6x40 default: 0000_0000h attribute: read-only. ac 97 modem controller modem in descriptor shadow devb:6x44 default: 0000_0000h attribute: read-only. bits description 31:16 subsysid. this register should be implemented for any function that could be instantiated more than once in a given system. for example, a system with 2 audio subsystems, one down on the motherboard and the other plugged into a pci expansion slot, should have this register implemented. this register, in combination with the subsystem vendor id register, enable the operating environment to distinguish one audio subsystem from the other(s). 15:0 subvenid. this register should be implemented for any function that could be instantiated more than once in a given system. for example a system with 2 audio subsystems, one down on the motherboard and the other plugged into a pci expansion slot, should have this register implemented. this register, in combination with the subsystem id register, enable the operating environment to distinguish one audio subsystem from the other(s). bits description 15:11 read-only. 10:8 intpin. indicates which pci interrupt pin is used for the ac '97 modem interrupt . read-only. hardwired to 010b to select pirqb_l. 7:0 intline. read-write. this data is not used by hardware. it is used to communicate across software the interrupt line that the interrupt pin is connected to. bits description 31:1 descr. descriptor current value . this is a test register for reading the current descriptor value. 0 read-only. bits description 31:1 descr. descriptor current value . this is a test register for reading the current descriptor value. 0 read-only. chapter 4 registers 267 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 4.8.2.2 ac '97 modem mixer registers the modem mixer registers are physically located in the codec. accesses to these registers are forwarded through the ac link to the codec. writes to a codec are completed when the data are inserted in the output slot. reads from a codec cause a pci retry cycle. for more information about these registers see the ac '97 spec. in the case of the split codec implementation (i.e., separate primary and secondary codecs), accesses to the modem mixer registers in different codecs are differentiated by the controller by using address offsets 00h?fh for the primary codec and address offsets 80h?fh for the secondary codec. table 63 on page 267 shows the register addresses for the modem mixer registers. these registers are exposed in i/o space. the base address register for these registers is devb:6x10. 4.8.2.3 ac '97 modem controller bus master registers these registers are exposed in i/o space and reside in the ac '97 controller. the two channels, modem in and modem out, each have their own set of bus mastering registers. the following register descriptions apply to both channels. table 63. modem mixer register address modem mixer registers primary secondary 1 00h:38h 80h:b8h reserved 3ch bch extended modem id 3eh beh extended modem stat/ctrl 40h c0h line 1 dac/adc rate 42h c2h line 2 dac/adc rate 2 44h c4h handset dac/adc rate 2 46h c6h line 1 dac/adc level mute 48h c8h line 2 dac/adc level mute 2 4ah cah handset dac/adc level mute 2 4ch cch gpio pin con g 4eh ceh gpio polarity/type 50h d0h gpio pin sticky 52h d2h gpio pin wake up 54h d4h gpio pin status 56h d6h misc. modem afe stat/ctrl 58h d8h vendor reserved 3 7ah fah vendor reserved 3 7ch fch vendor id1 3 7eh feh vendor id2 3 notes: 1. the ic supports a modem codec as either primary or secondary codec, but does not support two modem codecs. 2. registers 42h, 44h, 48h, 4ah, c2h, c4h, c8h, and cah are for functions not supported by the ic. 3. registers 58h, 7ah, 7ch, 7eh, d8h, fah, fch, and feh are multiplexed between audio and modem functions. 268 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information the base address register for these registers is devb:6x14. see section 4.1.2 on page 136 for a description of the register naming convention. the global control (mc3c), global status (mc40), codec access semaphore (mc44) registers are aliased to the same global registers in the audio and modem i/o space. therefore, a read-write to these registers in either audio or modem i/o space affects the same physical register. the following status and con?uration bits are powered by the vdd_corex well: mc40[md3] mc40[ad3] ac 97 modem controller buffer descriptor list base address mc00, mc10 default: 0000_0000h attribute: see below. table 64. modem bus master registers mnemonic name default mc00 modem in buffer descriptor list base address 0000_0000h mc04 modem in current index value 00h mc05 modem in last valid index 00h mc06 modem in status 0001h mc08 modem in position in current buffer 0000h mc0a modem prefetch index value 00h mc0b modem in control 00h mc10 modem out buffer descriptor list base address 0000_0000h mc14 modem out current index value 00h mc15 modem out last valid 00h mc16 modem out status 0001h mc18 modem out position in current buffer 0000h mc1a modem out prefetched index 00h mc1b modem out control 00h mc3c global control 0000_0000h mc40 global status 0030_0000h mc44 codec access semaphore 00h mc48 gpio pin status 0000h bits description 31:3 bdlba. buffer descriptor list base address . read-write. these bits represent address bits 31:3. the entries should be aligned on 8 byte boundaries. 2:0 read-only. chapter 4 registers 269 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information ac 97 modem controller current index value mc04, mc14 default: 00h attribute: see below. ac 97 modem controller last valid index mc05, mc15 default: 00h attribute: see below. ac 97 modem controller status mc06, mc16 default: 0001h attribute: see below. bits description 7:5 read-only. 4:0 civ. current index value . read-only. these bits represent which buffer descriptor within the list of 32 descriptors is being processed currently. as each descriptor is processed, this value is incremented. bits description 7:5 read-only. 4:0 lvi. read-write. these bits indicate the last valid descriptor in the list. this value is updated by the software as it prepares new buffers and adds to the list. bits description 15:5 reserved. 4 fifoerr. read-write. fifo error. the hardware sets this bit if an under-run or over-run occurs. this bit is cleared by writing a 1 to this bit position. 3 bcis. read-write. buffer completion interrupt status. this bit is set by the hardware after the last sample of a buffer has been processed, and if the interrupt on completion (ioc) bit is set in the command byte of the buffer descriptor. remains active until software clears bit. this bit is cleared by writing a 1 to this bit position. 2 lvbci. read-write. last valid buffer completion interrupt. this bit is set to 1 by hardware when last valid buffer has been processed. it remains active until cleared by software. this bit indicates the occurrence of the event signi ed by the last valid buffer being processed. thus, this is an event status bit that can be cleared by software once this event has been recognized. this event causes an interrupt if the enable bit in the control register is set. this bit is cleared by writing a 1 to this bit position. 1 celv. read-only. current equals last valid. 1 = current index is equal to the value in the last valid index register, and the buffer pointed to by the civ has been processed (i.e., after the last valid buffer has been processed). this bit is very similar to bit 2, except this bit re ects the state rather than the event. this bit re ects the state of the controller, and remains set until the controller exits this state. hardware clears this bit when controller exits state (i.e., until a new value is written to the lvi register). 0 bmch. read-only. bus master controller halted. this bit is set to 1b because of the run/pause bit being cleared in which case bmch may or may not be asserted immediately, depending on whether a pci transaction had previously been requested. if a pci transaction had previously been requested, bmch assertion occurs after completion of the single transaction. bus master controller halted can also happen once the controller has processed the last valid buffer in which case it sets mcx6[celv] and halts. this bit is cleared and the bus master controller resumes operation when both the run/ pause bit is set and the controller has exited the mcx6[celv] status. 270 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information notes: 1. modem in: fifo error indicates a fifo overrun. the fifo pointers don't increment, the incoming data is not written into the fifo, thus is lost. 2. modem out: fifo error indicates a fifo under-run. the sample transmitted in this case should be the last valid sample. ac 97 modem controller position in current buffer mc08, mc18 default: 0000h attribute: read-only. ac 97 modem controller prefetched index value mc0a, mc1a default: 00h attribute: read-only. ac 97 modem controller control register mc0b, mc1b default: 00h attribute: see below. bits description 15:0 picb. position in current buffer . these bits represent the number of samples left to be processed in the current buffer. bits description 7:5 read-only. 4:0 piv. these bits represent which buffer descriptor in the list has been prefetched. bits description 7:5 reserved 4 iocen. interrupt on completion enable . read-write. this bit controls whether or not an interrupt occurs when a buffer completes with the ioc bit set in its descriptor. 1 = enable. 0 = disable; bit 3 in the status register is still set, but the interrupt does not occur. chapter 4 registers 271 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information ac 97 modem controller global control mc3c default: 0000_0000h attribute: see below. 3 feien. fifo error interrupt enable . read-write. this bit controls whether the occurrence of a fifo error causes an interrupt or not. 1 = enable. 0 = disable; bit 4 in the status register is set, but the interrupt does not occur. 2 lvbien. last valid buffer interrupt enable . read-write. this bit controls whether the completion of the last valid buffer causes an interrupt or not. 1 = enable. 0 = disable; bit 2 in the status register is still set, but the interrupt does not occur. 1 regrst. register reset .read-write . 1 = contents of all registers of the bus master engine including the fifos are reset, except the interrupt enable bits (bits 4,3,2 of this register). software needs to set this bit. it must be set only when the run/pause bit runbm is cleared and mcx6[bmch] is asserted. setting it when either runbm is asserted (set) or when mcx6[bmch] is de-asserted (clear) causes unde ned consequences. this bit is self-clearing (software need not clear it). 0 = removes reset condition. 0 runbm. run/pause bus master . read-write. 1 = enable bus master operation. 0 = disable bus master; this results in all state information being retained (i.e., master mode operation can be stopped and then resumed). bits description 31:22 reserved 21:20 pcm46en . pcm 4/6 enable . read-write. con gures pcm output for 2, 4 or 6 channel mode 00 = 2-channel mode (default) 01 = 4 channel mode 10 = 6 channel mode 11 = reserved 19:6 reserved 5 srien. secondary resume interrupt enable . read-write. 1 = enable an interrupt to occur when the secondary codec causes a resume event on the ac link. 0 = disable interrupt. 4 prien. primary resume interrupt enable . read-write. 1 = enable an interrupt to occur when the primary codec causes a resume event on the ac-link. 0 = disable interrupt. bits description 272 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information ac 97 modem controller global status mc40 default: 0030_0000h attribute: see below. 3 shutoff. aclink shut off . read-write. 1 = disable the ac-link signals (drive all ac 97 outputs low and ignore all ac 97 input buffer enables). 0 = enable the ac-link signals. wake-up event detection is independent of this bit. 2 wrst. ac 97 warm reset . read-write. writing a 1 to this bit causes a warm reset to occur on the ac-link. the warm reset awakens a suspended codec without clearing its internal registers. if software attempts to perform a warm reset while acclk is running, the write is ignored and the bit is not changed. a warm reset can only occur in the absence of acclk. this bit is self-clearing (it clears itself after the reset has occurred and acclk has started). 1 crst_l. ac 97 cold reset, active low . read-write. writing to 0 to this bit causes a cold reset to occur on the ac-link. all data in the codec is lost. software needs to set this bit no sooner than after 1 s has elapsed. this bit re ects the state of the acrst_l pin. this bit is cleared to 0 upon entering s3/s4/s5 sleep states, and by sm_reset_l and reset_l assertions. 0 gpiien. gpi interrupt enable . read-write. this bit controls whether the change in status of any gpi (general purpose input/output, con gured as an input) causes an interrupt. 1 = the change on value of a gpi causes an interrupt and sets bit 0 of the global status register. 0 = bit 0 of the global status register is set, but an interrupt is not generated. bits description 31:22 reserved 21 pcm6cap. 6 channel capability .read-only. hardwired to 1. 0 = ac 97 doesn t support 6-channel audio output. 1 = ac 97 supports 6-channel audio output. 20 pcm4cap. 4 channel capability . read-only. hardwired to 1. 0 = ac 97 doesn t support 4-channel audio output. 1 = ac 97 supports 4-channel audio output. 19:18 reserved 17 md3. power down semaphore for modem . read-write. this bit is used by software in conjunction with the ad3 bit to coordinate the entry of the two codecs into d3 state. this bit resides in the vdd_corex well and maintains context across power states. this bit has no hardware function. 16 ad3. power down semaphore for audio . read-write. this bit is used by software in conjunction with the md3 bit to coordinate the entry of the two codecs into d3 state. this bit resides in the vdd_corex well and maintains context across power states. this bit has no hardware function. 15 rcstat. read complete status . read-write. this bit indicates the status of codec read completions. 1 = codec read failed due to one of the following errors: a time-out, or that acclk is detected to not be operating adequately. this bit remains set until being cleared by software. 0 = codec read completes normally. this bit is cleared by writing a 1 to this bit position. 14 s12bit3. bit 3 of slot 12: display bit 3 of the most recent slot 12 from modem codec . 13 s12bit2. bit 2 of slot 12: display bit 2 of the most recent slot 12 from modem codec . 12 s12bit1. bit 1 of slot 12: display bit 1 of the most recent slot 12 from modem codec . chapter 4 registers 273 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information ac 97 modem controller codec access semaphore mc44 default: 00h attribute: see below. 11 srint. secondary resume interrupt . read-write. this bit indicates that a resume event occurred on acsdi[1]. 1 = resume event occurred. cleared by writing a 1 to this bit position. 10 print. primary resume interrupt . read-write. this bit indicates that a resume event occurred on acsdi[0]. 1 = resume event occurred. cleared by writing a 1 to this bit position. 9 scrdy. secondary codec ready . read-only. re ects the state of the codec ready bit in acsdi[1]. bus masters ignore the condition of the codec ready bits. software must check this bit before starting the bus masters. this bit is cleared with assertion of mc3c[shutoff]. this bit is also cleared when acclk is detected to not be operating adequately. 8 pcrdy. primary codec ready . read-only. re ects the state of the codec ready bit in acsdi[0]. bus masters ignore the condition of the codec ready bits. software must check this bit before starting the bus masters. this bit is cleared with assertion of mc3c[shutoff]. this bit is also cleared when acclk is detected to not be operating adequately. 7 micint. mic in interrupt . read-only. this bit indicates that one of the mic in channel interrupts occurred. 1 = interrupt occurred. when the speci c interrupt is cleared, this bit is cleared automatically. 6 point. pcm out interrupt . read-only. his bit indicates that one of the pcm out channel interrupts occurred. 1 = interrupt occurred. when the speci c interrupt is cleared, this bit is cleared automatically. 5 piint. pcm in interrupt . read-only. this bit indicates that one of the pcm in channel interrupts occurred. 1 = interrupt occurred. when the speci c interrupt is cleared, this bit is cleared automatically. 4 reserved 3 reserved 2 moint. modem out interrupt . read-only. this bit indicates that one of the modem out channel interrupts occurred. 1 = interrupt occurred. when the speci c interrupt is cleared, this bit is cleared automatically. 1 miint. modem in interrupt . read-only. this bit indicates that one of the modem in channel interrupts occurred. 1 = interrupt occurred. when the speci c interrupt is cleared, this bit is cleared automatically. 0 gpiint. gpi status change interrupt . read-write. this bit is set whenever bit 0 of slot 12 is set. this happens when the value of any of the gpios currently de ned as inputs changes. if 1 this bit sets also pm20[ac97_sts]. 1 = input changed. this bit is cleared by writing a 1 to this bit position. bits description 7:1 reserved 0 cas. codec access semaphore . read-write. this bit is read by software to check whether a codec access is currently in progress. the act of reading this register sets this bit to 1. the driver that reads this bit can then perform a codec i/o access. once the access is completed, or if acclk is detected to not be operating adequately, hardware automatically clears this bit. 0 = no access in progress. if and only if cas = 1 and a codec access has not yet been requested (i.e., the pci transaction has not yet been initiated), cas may be cleared by writing a 0 to this bit position. bits description (continued) 274 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information ac 97 modem gpio statusmc48 default:00h attribute: read-only. 4.9 usb controller registers 4.9.1 usb open host controller registers 4.9.1.1 usb open host controller con guration registers (dev0:[1:0]xxx) these registers are located in pci con?uration space on the secondary pci interface, device 0 (function 0 and 1 for each of the two ohci controllers). see section 4.1.2 on page 136 for a description of the register naming convention. bits description 15:0 gpio. mirror register updated automatically with each valid slot 12 input to re ect or mirror the current state of the modem codec gpio pins. chapter 4 registers 275 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information usb controller vendor and device id register dev0:[1:0]x00 default: 7464_1022h. attribute: read-only. usb controller status and command register dev0:[1:0]x04 default: 0280_0000h. attribute: see below. usb revision id, programming interface, sub class and base registers dev0:[1:0]x08 default: 0c03_10xxh see below. attribute: read-only. usb controller bist, header, latency, and cacheline size register dev0:0x0c bits description 31:16 usb controller device id. 15:0 vendor id. bits description 31:30 reserved. 29 signaled master abort. read; write 1 to clear. this bit is set high by the hardware when a bus master cycle is terminated with a master abort. 28 received target abort. read; write 1 to clear. this bit is set high by the hardware when a target abort command is received during a master cycle. 27 reserved. 26:25 devsel timing. read-only. these bits are xed at 01b and speci es medium timing as de ned by the pci speci cation. 24:9 read-only. these bits are xed at their default values. 8 serr_l detection enable. read-write. this bit has no effect on the hardware. 7:5 reserved. 4 memory write and invalidate enable. read-write. 1=enables bus master to issue memory write and invalidate cycles. 3 reserved. 2 bus master enable. read-write. 1=enables bus master capability. 1 memory space enable. read-write. 1=enables access to the memory space for this device (the host controller registers). 0 i/o space enable. read-write. 1=enables access to the i/o space for this device (the keyboard/ mouse controller ports for legacy emulation). bits description 31:24 baseclass. 23:16 subclass. 15:8 progif. 7:0 revisionid. the value of this register is revision-dependent. 276registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information default: 0080_0000h. attribute: see below. usb controller bist, header, latency, and cacheline size register dev0:1x0c default: 0000_0000h. attribute: see below. usb controller base address register dev0:[1:0]x10 default: 0000_0000h. attribute: see below. usb subsystem id and subsystem vendor id register dev0:[1:0]x2c default: 0000_0000h. attribute: read-only. controller interrupt line, interrupt pin, min. grant, max latency register dev0:[1:0]x3c default: 5000_04ffh. attribute: read-only. bits description 31:24 bist. read-only. these bits xed at their default values. 23:16 header. read-only. these bits xed at their default values. 15:8 latency. bits[7:3] are read-write; bits[2:0] are read-only at their default value. 7:0 cache. read-write. 08h=32 bytes, 00h=0 bytes. no other values are allowed. bits description 31:24 bist. read-only. these bits xed at their default values. 23:16 header. read-only. these bits xed at their default values. 15:8 latency. bits[7:3] are read-write; bits[2:0] are read-only at their default value. 7:0 cache. read-write. 08h=32 bytes, 00h=0 bytes. no other values are allowed. bits description 31:12 base[31:12] base address. read-write. these bits specify a 4-kilobyte non-prefetchable space that can be placed anywhere in 32-bit memory. 11:0 read-only. these bits xed at their default values. bits description 31:16 ssid. subsystem id register. this eld is write accessible through dev0:0x70. 15:0 ssvendorid. subsystem vendor id register. this eld is write accessible through dev0:0x70. bits description 31:24 max latency. read-only. this register indicates how often the usb controller requires host accesses. the value 50h indicates 20 microseconds. 23:16 min gnt. read-only. these bits are xed at their default values. 15:8 interrupt pin. read-only. the value 04h indicates that usb interrupts are routed through pirqd_l 7:0 interrupt line. read-write. this eld controls no hardware. chapter 4 registers 277 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information usb buffer control register dev0:[1:0]x44 default: 0000h. attribute: read-write. usb device and subsystem id read-write register dev0:[1:0]x70 default: 0000_0000h. attribute: read-write. 4.9.1.2 usb open host controller memory-mapped registers 4.9.1.2.1 summary for a complete description of these registers, see the ochi 1.0a speci?ation. the base address is controlled by dev0:[1:0]x10. bits description 15:9 reserved. 8 pipdis. sie pipelining disable. read-write. 1=transfer descriptors are disabled from being pipelined with usb bus activity. 7:1 reserved. 0 db16. data buffer region 16. read-write. 1=the size of the region for the data buffer is 16 bytes. 0=the region is 32 bytes. bits description 31:16 ssid. subsystem id register. the value placed in this register is visible in dev0:0x2c[31:16]. 15:0 ssvendorid. subsystem vendor id register. the value placed in this register is visible in dev0:0x2c[15:0]. table 65. usb ohci memory-mapped register summary offset register offset register 00-03 hcrevision 34-37 hcfminterval 04-07 hccontrol 38-3b hcframeremaining 08-0b hccommandstatus 3c-3f hcfmnumber 0c-0f hcinterruptstatus 40-43 hcperiodicstart 10-13 hcinterruptenable 44-47 hclsthreshold 14-17 hcinterruptdisable 48-4b hcrhdescriptora 18-1b hchcca 4c-4f hcrhdescriptorb 1c-1f hcperiodcurrented 50-53 hcrhstatus 20-23 hccontrolheaded 54-57 hcrhportstatus[1] 24-27 hccontrolcurrented 58-5b hcrhportstatus[2] 28-2b hcbulkheaded 5c-5f hcrhportstatus[3] 2c-2f hcbulkcurrented 30-33 hcdonehead 100 hcecontrol 104 hceinput 108 hceoutput 10c hcestatus 278 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 4.9.1.2.2 implementation-speci? items hcrevision[7:0] is 10h to indicate that it conforms to ohci 1.0. hcrevision[8] is 1 to indicate that legacy keyboard & mouse emulation support is present. hcfminterval_fslargestdatapacket resets to 0. hcrhdescriptora_numberdownstreamports is hardwired to 3. hcrhdescriptora_nopowerswitching resets to 1. hcrhdescriptora_powerswitchingmode and hcrhdescriptora_overcurrentprotectionmode must not be set and reset to 0. hcrhdescriptora_powerontopowergoodtime resets to 1 (representing 2 ms), and can only hold the values 0 to 3 (0 to 6 ms). hcrhdescriptora_noovercurrentprotection resets to 0. hcrhdescriptorb_deviceremovable resets to 0 and should be set by bios if non-removable devices are attached. hcrhdescriptorb_portpowercontrolmask resets to 0 and should not be set. because power switching is not implemented, the set and clear power bits in hcrhstatus and hcrhportstatus[1-3] are not supported. hcecontrol and hcestatus reset to 00h. hceinput and hceoutput are not reset. hcdonehd[31:4] should not be modi?d. hcfminterval_fslargestdatapacket is limited to 14 bits. bit 15 is read-only 0. hcfmnumber should not be modi?d. chapter 4 registers 279 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 4.9.2 usb enhanced host controller registers 4.9.2.1 usb enhanced host controller con guration registers (dev0:2xxx) usb device and vendor id dev0:2x00 default: 7463_1022h. attribute: read-only. usb status and command dev0:2x04 default: 0210_0000h. attribute: see below. bits description 31:16 devid. device id . this value is hardwired to 7463h 15:0 venid. vendor id . this is hardwired to amdid (1022h). bits description 31:27 stat. pci status bits . read-only. hardwired to 0b. 26:25 devsel. d evsel timing . read-only. hardwired to 01b. 24 mdped. master data parity error detected . read-only. hardwired to 0b. 23 fbbc. fast back-to-back capable . read-only.hardwired to 0b. 22 reserved. hardwired to 0b. 21 m66en. 66 mhz capable. read-only. hardwired to 0b. 20 caplst. capabilities list . read-only. hardwired to 1b to indicate that there is a capabilities list (debug port). 19:10 reserved. hardwired to 000h. 9:3 cmd. pci command bits . read-only. hardwired to 00h. 2 bmen. bus master enable . read-write. when set to 1b the device is allowed to act as a bus master. 1 memen. memory space enable . read-write. when set to 1b the device responds to memory space accesses. 0 ioen. i/o space enable . read-only. hardwired to 0b, i.e., the device never responds to i/o accesses. 280 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information usb class and revision id dev0:2x08 default: 0c03_20xxh attribute: read-only usb bist, header, latency, and cache line size dev0:2x0c default: 0000_0000h. attribute: see below. usb register space base address dev0:2x10 default: 0000_0000h. attribute: see below. usb subsystem id and subsystem vendor id dev0:2x2c bits description 31:24 baseclass. base class code . hardwired to 0ch = serial bus controller. 23:16 scc. sub-class code . hardwired to 03h = universal serial bus controller. 15:8 pi. programming interface . hardwired to 20h = usb 2.0 host controller conforming to ehci spec. 7:0 revid. revision id . the value of this register is revision-dependent. bits description 31:24 bist. read-only. hardwired to 0b. 23:16 header. read-only. hardwired to 00h to indicate a normal device header. 15:8 latency. read-write. this register controls no internal hardware. 7:0 cls. cache line size . read-only. this register controls no internal hardware. bits description 31:8 bar. base address . read-write. corresponds to memory address [31:8]. allows for a register space of 256 bytes. 7:4 reserved. hardwired to 0h. 3 prf. prefetchable . read-only. hardwired to 0b = not prefetchable. 2:1 tpye. type. read-only. hardwired to 00b = may only be mapped into 32-bit address space. 0 msi. memory space indicator . read-only. hardwired to 0b = memory-mapped. chapter 4 registers 281 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information default: 7463_1022h. attribute: read-only. usb capabilities pointer dev0:2x34 default: 0000_0080h. attribute: read-only. usb latency and interrupt control dev0:2x3c default: 0000_04ffh. attribute: see below. usb legacy support extended capabilities dev0:2x40 bits description 31:16 subsysid. subsystem id . this value is writable through dev0:2x70[31:16]. 15:0 subvenid. subvendor id . this value is writable through dev0:2x70[15:0]. bits description 31:8 reserved. hardwired to 000000h. 7:0 cptr. capabilities pointer . hardwired to 80h, to point to debug port registers. bits description 31:24 maxlat. max_lat . read-only. hardwired to 00h to indicate no special requirements for latency timers. 23:16 mingnt. min_gnt . read-only. hardwired to 00h to indicate no special requirements for latency timers. 15:8 intpin. interrupt pin . read-only. hardwired to 04h, to indicate usage of pirqd_l. 7:0 intline. interrupt line . read-write. only used by sw to determine interrupt routing, not used by ehc hardware. 282 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information default: 0000_0001. attribute: see below. this register is used by pre-os software (bios) and the operating system to coordinate ownership of the ehci host controller. bits description 31:25 reserved. hardwired to 00h. 24 hcos. hc os owned semaphore . read-write. system software sets this bit to request ownership of the ehci controller. ownership is obtained when this bit reads as 1 and the hc bios owned semaphore bit reads as clear. this bit resides in the aux power domain. 23:17 reserved. hardwired to 00h. 16 hcbios. hc bios owned semaphore . read-write. the bios sets this bit to establish ownership of the ehci controller. system bios clears this bit in response to a request for ownership of the ehci controller by system software. this bit resides in the aux power domain. 15:8 neecp. next ehci extended capability pointer . read-only. this eld points to the pci con guration space offset of the next extended capability pointer. a value of 00h indicates the end of the extended capability list. 7:0 capid. capability id . read-only. this eld identi es the extended capability. a value of 01h identi es the capability as legacy support. this extended capability requires one additional 32-bit register for co-status information, and this register is located at dev0:2x44. chapter 4 registers 283 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information usb legacy support control/status dev0:2x44 default: 0000_0000h. attribute: see below. bits description 31 smibar. smi on bar . read; write 1 to clear. this bit is set to 1b whenever the base address register (bar) at dev0:2x10 is written. 30 smicmd. smi on pci command . read; write 1 to clear. this bit is set to 1b whenever the pci command register is written. 29 smioc. smi on os ownership change . read; write 1 to clear. this bit is set to 1b whenever the hc os owned semaphore bit in the dev0:2x40 register transitions from 1 to a 0 or 0 to a 1. 28:22 reserved. hardwired to 00h. 21 smiaa. smi on async advance . read-only. shadow bit of the interrupt on async advance bit in the ecap34 register. 20 smihse. smi on host system error . read-only. shadow bit of host system error bit in the ecap34 register. 19 smiflr. smi on frame list rollover . read-only. shadow bit of frame list rollover bit in the ecap34 register. 18 smipcd. smi on port change detect . read-only. shadow bit of port change detect bit in the ecap34 register. 17 smiuerr. smi on usb error . read-only. shadow bit of usb error interrupt (usberrint) bit in the ecap34 register. 16 smiuc. smi on usb complete . read-only. shadow bit of usb interrupt (usbint) bit in the ecap34 register. 15 smibaren. smi on bar enable . read-write. when this bit is 1b and smi on bar is 1b, then the host controller issues an smi. this bit resides in the aux power domain. 14 smicmden. smi on pci command enable . read-write. when this bit is 1b and smi on pci command is 1b, then the host controller issues an smi. this bit resides in the aux power domain. 13 smiosen. smi on os ownership enable . read-write. when this bit is a one and the os ownership change bit is one, the host controller issues an smi this bit resides in the aux power domain. 12:6 reserved. hardwired to 00h. 5 smiaaen. smi on async advance enable . read-write. when this bit is a one, and the smi on async advance bit (above) in this register is a one, the host controller issues an smi immediately. this bit resides in the aux power domain. 284 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information pre-os (bios) software uses this register to enable smis for every ehci/usb event it needs to track. bits [21:16] of this register are simply shadow bit of ecap34 register [5:0]. 4 smihseen. smi on host system error enable . read-write. when this bit is a one, and the smi on host system error bit (above) in this register is a one, the host controller issues an smi immediately. this bit resides in the aux power domain. 3 smiflren. smi on frame list rollover enable . read-write. when this bit is a one, and the smi on frame list rollover bit (above) in this register is a one, the host controller issues an smi immediately. this bit resides in the aux power domain. 2 smipcden. smi on port change enable . read-write. when this bit is a one, and the smi on port change detect bit (above) in this register is a one, the host controller issues an smi immediately. this bit resides in the aux power domain. 1 smiueen. smi on usb error enable . read-write. when this bit is a one, and the smi on usb error bit (above) in this register is a one, the host controller issues an smi immediately. this bit resides in the aux power domain. 0 usmien. usb smi enable . read-write.when this bit is a one, and the smi on usb complete bit (above) in this register is a one, the host controller issues an smi immediately. this bit resides in the aux power domain. bits description chapter 4 registers 285 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information usb port wake capabilities, frame length adjustment, and serial bus release number dev0:2x60 default: 0001_2020h. attribute: see below. usb subsystem id and subsystem vendor id rw alias dev0:2x70 default: 7463_1022h. attribute: read-write. usb debug port capability register dev0:2x80 bits description 31:16 portwakecap. port wake up capability mask . read-write. a 1b in bit position [16] indicates that the register is implemented. bit positions [17] through [31] correspond to a physical port.these bits reside in the aux power domain. 15:14 reserved bits. hardwired to 0b. 13:8 fladj. frame length adjustment register . read-write. the sof cycle time is equal to 59488 + (16 this v alue). the default of 20h gives a sof cycle time of 60000. frame length (hs bit times) fladj value 59488 00h 59504 01h 59520 02h 59984 1fh 60000 20h 60480 3eh 60496 3fh these bits reside in the aux power domain. 7:0 serial bus speci cation release number (sbrn). read-only. hardwired to 20h = release 2.0 bits description 31:16 subsysid. subsystem id . this value is read-only at dev0:2x2c[31:16]. reset default: 7463h 15:0 subvenid. subvendor id . this value is read-only at dev0:2x2c[15:0]. reset default: 1022h 286registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information default: 20c0_880ah. attribute: read-only. usb power management capability register dev0:2x88 default: fe82_0001h. attribute: read-only. bits description 31:29 dpbar. debug port bar . a 3-bit eld, which indicates which one of the possible 6 base address register offsets contains the debug port registers. hardwired to 1h to indicate the use of the bar at dev0:2x14 28:16 dpoff. debug port offset . hardwired to c0h 15:8 nxt_ptr. next pointer . pointer to the next item in the capabilities list. hardwired to 88h (due to power management capability). 7:0 cap_id.the value of 0ah in this eld identi es that the function supports a debug port . bits description 31:27 pmecap. pme_support . this 5-bit eld indicates the power states in which the function may assert pme_l. a value of 0b for any bit indicates that the function is not capable of asserting the pme_l signal while in that power state. 26 d2cap. d2 support . if this bit is a 1, this function supports the d2 power management state. 25 d1cap. d1 support . if this bit is a 1, this function supports the d1 power management state. 24:22 auxcur. aux_current . this 3 bit eld reports the 3.3vaux auxiliary current requirements for the pci function. [24:22] max. current required 1 1 1 375 ma 1 1 0 320 ma 1 0 1 270 ma 1 0 0 220 ma 0 1 1 160 ma 0 1 0 100 ma 0 0 1 55 ma 0 0 0 0 (self powered) 21 dsi.the device speci c initialization bit indicates whether special initialization of this function is required (beyond the standard pci con guration header) before the generic class device driver is able to use it. 20 reserved. hardwired to 0b. chapter 4 registers 287 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 19 pmeclk. pme clock . when this bit is a 1, it indicates that the function relies on the presence of the pci clock for pme_l operation. when this bit is a 0, it indicates that no pci clock is required for the function to generate pme_l. 18:16 ver. version . a value of 010b indicates that this function complies with revision 1.1 of the pci power management interface speci cation. 15:8 nxt_ptr.next pointer . pointer to the next item in the capabilities list. hardwired to 00h. 7:0 cap_id.capability id. the value of 01h identi es the linked list item as being the pci power management registers. bits description 288 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information usb power management control/status & data register dev0:2x8c default: 0000_0100h. attribute: see below. usb remote wake-up mode dev0:2xa0 bits description 31:24 data. data . read-only. this register is used to report the state dependent data requested by the data_select eld. 23:16 p2pcap. pci to pci bridge support extensions . read-only. not used, hardwired to 00h. 15 pmestat. pme_status . read; write 1 to clear. this bit is set when the function would normally assert the pme_l signal independent of the state of the pme_en bit. this bit resides in the aux power domain. 14:13 data_scale. data_scale . read-only. this 2-bit read-only eld indicates the scaling factor to be used when interpreting the value of the data register. not used, hardwired to 00b. 12:9 data_select. data_select . read-only. this 4-bit eld is used to select which data is to be reported through the data register and data_scale eld. not used, hardwired to 0h. 8 pme_en. an 1b enables the function to assert pme_l. when 0b, pme_l assertion is disabled. this bit resides in the aux power domain. 7:2 reserved. hardwired to 00h. 1:0 pwrstat. powerstate . this 2-bit eld is used both to determine the current power state of a function and to set the function into a new power state. the de nition of the eld values is given below. 00b d0 01b d1 10b d2 11b d3hot these bits reside in the aux power domain. chapter 4 registers 289 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information default: 0000_0000h. attribute: see below. 4.9.2.1.1 memory-mapped registers 4.9.2.1.2 host controller capability registers these registers are located in memory-mapped io space. the base address register for these registers is dev0:2 bits description 31:1 reserved. hardwired to 00000000h. 0 rwm. remote wake-up mode . read-write. this bit controls the behavior of the host controller when not in power state d0. when set to 1b the host controller immediately drives resume on all its suspended ports. when cleared to 0b the host controller only latches the wake-up event in the respective port status register (ecap[88:74]) and postpones the resume until the system is back to d0 (s0). this bit resides in the aux power domain. 290 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 4.9.2.2 usb enhanced host controller memory-mapped registers usb hc version and capability length ecap00 default: 0100_0030h. attribute: read-only. usb hc structural parameters ecap04 default: 0010_2306h. attribute: read-only. bits description 31:16 hciversion. interface version number . default = 0100h = rev. 0.96 in bcd. 15:8 reserved. hardwired to 00h. 7:0 caplength. capability registers length . offset to add to dev0:2x10 to nd operational registers. bits description 31:24 reserved. hardwired to 00h. 23:20 dpnum. debug port number . this register identi es which of the host controller ports is the debug port. the value is the port number (one-based) of the debug port. a non-zero value in this eld indicates the presence of a debug port. 19:17 reserved. hardwired to 000b. 16 p_indicator. port indicators . this bit indicates whether the ports support port indicator control. hardwired to 0b, since there is no such support. 15:12 n_cc. number of companion controller . this eld indicates the number of companion controllers associated with this usb 2.0 host controller. hardwired to 2h. 11:8 n_pcc. number of ports per companion controller . this eld indicates the number of ports supported per companion host controller. it is used to indicate the port routing con guration to system software. hardwired to 3h. chapter 4 registers 291 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 7 prr. port routing rules . this eld indicates the method used by this implementation for how all ports are mapped to companion controllers. hardwired to 0b = the rst n_pcc ports are routed to the lowest numbered function companion host controller, the next n_pcc port are routed to the next lowest function companion controller, and so on. 6:5 reserved. hardwired to 00b. 4 ppc. port power control . this eld indicates whether the host controller implementation includes port power control. hardwired to 0b, since there is no power control. 3:0 n_ports.number of ports . this eld speci es the number of physical downstream ports implemented on this host controller. the value of this eld determines how many port registers are addressable in the operational register space. hardwired to 6h. bits description 292 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information usb hc capability parameters ecap08 default: 0000_4082h. attribute: read-only. usb command register ecap30 bits description 31:16 reserved. hardwired to 0b. 15:8 eecp. ehci extended capabilities pointer . this optional eld indicates the existence of a capabilities list. a value of 00h indicates no extended capabilities are implemented. a non-zero value in this register indicates the offset in pci con guration space of the rst ehci extended capability. the pointer value must be 40h or greater if implemented to maintain the consistency of the pci header de ned for this class of device. 7:4 ist. isochronous scheduling threshold . this eld indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. when bit [7] is zero, the value of the least signi cant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before ushing the state. when bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame. 3 reserved. hardwired to 0b. 2 aspc. asynchronous schedule park capability . hardwired to 0b = the host controller supports the park feature for high-speed queue heads in the asynchronous schedule. the feature can be disabled or enabled and set to a speci c level by using the asynchronous schedule park mode enable and asynchronous schedule park mode count elds in the ecap30 register. 1 pflf. programmable frame list flag . hardwired to 1b = system software can specify and use a smaller frame list and con gure the host controller through the ecap30 register frame list size eld. the frame list must always be aligned on a 4k page boundary. this requirement ensures that the frame list is always physically contiguous. 0 ac64. 64-bit addressing capability . hardwired to 0b = data structures using 32-bit address memory pointers. chapter 4 registers 293 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information default: 0008_0000h. attribute: see below. bits description 31:24 reserved. hardwired to 00h. 23:16 itc. interrupt threshold control . read-write. this eld is used by system software to select the maximum rate at which the host controller issues interrupts. the only valid values are de ned below. if software writes an invalid value to this register, the results are unde ned. value maximum interrupt interval 00h reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms) software modi cations to this bit while hchalted bit is equal to zero results in unde ned behavior. 15:12 reserved. hardwired to 0000b. 11 aspme. asynchronous schedule park mode enable . read-write. hard wired to =b, software uses this bit to enable or disable park mode. when this bit is one, park mode is enabled. when this bit is a zero, park mode is disabled. 10 reserved. hardwired to 0b. 9:8 aspmc. asynchronous schedule park mode count . read-write.hard wired to 0h, it contains a count of the number of successive transactions the host controller will execute from a high-speed queue head on the asynchronous schedule before continuing traversal of the asynchronous schedule. see ehci spec, section 4.10.3.2 for full operational details. valid values are 1h to 3h. software must not write a zero to this bit when park mode enable is a one as this results in unde ned behavior. 7 lite_hcreset. light host controller reset . read-write. it allows the driver to reset the ehci controller without affecting the state of the ports or the relationship to the companion host controllers. a host software read of this bit as zero indicates the light host controller reset has completed and it is safe for host software to re-initialize the host controller. a host software read of this bit as a one indicates the light host controller reset has not yet completed. 6 iaad. interrupt on async advance doorbell . read-write. this bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. software must write a 1b to this bit to ring the doorbell. 5 ase. asynchronous schedule enable . read-write. this bit controls whether the host controller skips processing the asynchronous schedule. 0= do not process the asynchronous schedule. 1= use the ecap48 register to access the asynchronous schedule. 294 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 4 pse. periodic schedule enable . read-write. this bit controls whether the host controller skips processing the periodic schedule. 0= do not process the periodic schedule. 1= use the ecap44 register to access the periodic schedule. 3:2 fls. frame list size . read-write. this eld speci es the size of the frame list. the size the frame list controls which bits in the frame index register should be used for the frame list current index. 00b 1024 elements (4096 bytes) default value 01b 512 elements (2048 bytes) 10b 256 elements (1024 bytes) for resource-constrained environments 11b reserved 1 hcreset. host controller reset. read-write. this control bit is used by software to reset the host controller. the effects of this on root hub registers are similar to a chip hardware reset. when software writes a one to this bit, the host controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediately terminated. a usb reset is not driven on downstream ports. pci con guration registers are not affected by this reset. all operational registers, including port registers and port state machines are set to their initial values. port ownership reverts to the companion host controller(s). software must reinitialize the host controller in order to return the host controller to an operational state. this bit is set to zero by the host controller when the reset process is complete. software cannot terminate the reset process early by writing a zero to this register. software should not set this bit to a one when the hchalted bit in the ecap34 register is a zero. attempting to reset an actively running host controller results in unde ned behavior. 0 rs. run/stop. read-write. 1= run. 0= stop. when set to a 1b, the host controller proceeds with execution of the schedule. the host controller continues execution as long as this bit is set to a 1b. when this bit is cleared to 0b, the host controller completes the current and any actively pipelined transactions on the usb and then halts. the host controller must halt within 16 microframes after software clears the run bit. the hc halted bit in the status register indicates when the host controller has nished its pending pipelined transactions and has entered the stopped state. software should not write a one to this eld unless the host controller is in the halted state (i.e., hchalted in the ecap34 register is a one). bits description chapter 4 registers 295 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information usb status register ecap34 default: 0000_1000h. attribute: see below. bits description 31:16 reserved. hardwired to 0000h. 15 ass. asynchronous schedule status . read-only. the bit reports the current real status of the asynchronous schedule. if this bit is a zero then the status of the asynchronous schedule is disabled. if this bit is a one then the status of the asynchronous schedule is enabled. 14 pss. periodic schedule status . read-only. the bit reports the current real status of the periodic schedule. if this bit is a zero then the status of the periodic schedule is disabled. if this bit is a one then the status of the periodic schedule is enabled. 13 rec. reclamation . this is a read-only status bit, which is used to detect an empty asynchronous schedule. 12 hch. hchalted . read-only. this bit is a zero whenever the run/stop bit is a one. the host controller sets this bit to one after it has stopped executing as a result of the run/stop bit being cleared to 0b, either by software or by the host controller hardware (e.g., internal error). 11:6 reserved. hardwired to 00h. 5 iaa. interrupt on async advance . read; write 1 to clear. system software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the interrupt on async advance doorbell bit in the ecap30 register. this status bit indicates the assertion of that interrupt source. 4 hse. host system error . read; write 1 to clear. the host controller sets this bit to 1b when a serious error occurs during a host system access involving the host controller module. when this error occurs, the host controller clears the run/stop bit in the command register to prevent further execution of the scheduled tds. 296registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 3 flr. frame list rollover . read; write 1 to clear. the host controller sets this bit to a one when the frame list index rolls over from its maximum value to zero. the exact value at which the rollover occurs depends on the frame list size. 2 pcd. port change detect . read; write 1 to clear. the host controller sets this bit to a one when any port for which the port owner bit is set to zero has a change bit transition from a zero to a one or a force port resume bit transition from a zero to a one as a result of a j-k transition detected on a suspended port. this bit is also set as a result of the connect status change being set to a one after system software has relinquished ownership of a connected port by writing a zero to a port s port owner bit. 1 usberrint. usb error interrupt . read; write 1 to clear. the host controller sets this bit to 1b when completion of a usb transaction results in an error condition (e.g., error counter under ow). if the td on which the error interrupt occurred also had its ioc bit set, both this bit and usbint bit are set. 0 usbint. usb interrupt . read; write 1 to clear. the host controller sets this bit to 1b on the completion of a usb transaction, which results in the retirement of a transfer descriptor that had its ioc bit set. the host controller also sets this bit to 1b when a short packet is detected (actual number of bytes received was less than the expected number of bytes). bits description chapter 4 registers 297 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information usb interrupt enable register ecap38 default: 0000_0000h. attribute: see below. usb frame index register ecap3c default: 0000_0000h. attribute: see below (only doubleword access supported). bits description 31:6 reserved. hardwired to 0000000h. 5 iaae. interrupt on async advance enable . read-write. when this bit is a one, and the interrupt on async advance bit in the ecap34 register is a one, the host controller issues an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing the interrupt on async advance bit. 4 hsee. host system error enable . read-write. when this bit is a one, and the host system error status bit in the ecap34 register is a one, the host controller issues an interrupt. the interrupt is acknowledged by software clearing the host system error bit. 3 flre. frame list rollover enable . read-write. when this bit is a one, and the frame list rollover bit in the ecap34 register is a one, the host controller issues an interrupt. the interrupt is acknowledged by software clearing the frame list rollover bit. 2 pcie. port change interrupt enable . read-write. when this bit is a one, and the port change detect bit in the ecap34 register is a one, the host controller issues an interrupt. the interrupt is acknowledged by software clearing the port change detect bit. 1 ueie. usb error interrupt enable . read-write. when this bit is a one, and the usberrint bit in the ecap34 register is a one, the host controller issues an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing the usberrint bit. 0 uie. usb interrupt enable . read-write. when this bit is a one, and the usbint bit in the ecap34 register is a one, the host controller issues an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing the usbint bit. bits description 31:14 reserved. hardwired to 0000h. 13:0 find. frame index . read-write. the value in this register increments at the end of each time frame (e.g., micro-frame). bits [n:3] are used for the frame list current index. this means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. ecap30[fls] number elementsn 00b (1024) 12 01b (512) 11 10b (256) 10 11b reserved 298 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information this register cannot be written unless the host controller is in the halted state as indicated by the hchalted bit (ecap34). a write to this register while the run/stop bit is set to a one (ecap30) produces unde?ed results. writes to this register also affect the sof value. usb control data structure segment register ecap40 default: 0000_0000h. attribute: read-only. usb periodic frame list base address register ecap44 default: 0000_0000h. attribute: see below (only doubleword access supported). the memory structure referenced by this physical memory pointer is assumed to be 4-kbyte aligned. the contents of this register are combined with the frame index register (ecap3c) to enable the host controller to step through the periodic frame list in sequence. usb current asynchronous list address register ecap48 default: 0000_0000h. attribute: see below (only doubleword access supported). the memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. bits description 31:0 hardwired to 00000000h, since no 64-bit capability implemented (see ecap08). bits description 31:12 bar. base address . read-write. these bits correspond to memory address signals [31:12], respectively. 11:0 reserved. hardwired to 000h. bits description 31:5 lpl. link pointer low . read-write. these bits correspond to memory address signals [31:5], respectively. this eld may only reference a queue head (qh). 4:0 reserved. hardwired to 00h. chapter 4 registers 299 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information usb con gure flag register ecap70 default: 0000_0000h. attribute: see below. usb port status and control register [6:1] ecap[88:74] default: 0000_3000h. attribute: see below. bits description 31:1 reserved. hardwired to 00000000h. 0 cf. con gure flag . read-write. host software sets this bit as the last action in its process of con guring the host controller. this bit controls the default port-routing control logic. bit values and side-effects are listed below. 0b port routing control logic default-routes each port to an implementation dependent classic host controller. 1b port routing control logic default-routes all ports to this host controller. this bit resides in the aux power domain. bits description 31:23 reserved. hardwired to 000h. 22 wkoc_e. wake on over-current enable . read-write. writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events this bit resides in the aux power domain. 21 wkdscnnt_e. wake on disconnect enable . read-write. writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. this bit resides in the aux power domain. 20 wkcnnt_e. wake on connect enable . read-write. writing this bit to a one enables the port to be sensitive to device connects as wake-up events. this bit resides in the aux power domain. 19:16 ptc. port test control . read-write. when this eld is zero, the port is not operating in a test mode. a non-zero value indicates that it is operating in test mode and the speci c test mode is indicated by the speci c value. the encoding of the test mode bits are (0110b 1111b are reserved): bits test mode 0000b test mode not enabled 0001b test j_state 0010b test k_state 0011b test se0_nak 0100b test packet 0101b test force_enable refer the usb speci cation revision 2.0, chapter 7 for details on each test mode. 15:14 pic. port indicator control . read-only. hardwired to 00b, since there is no support for this (see ecap04). 300 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 13 pown. port owner . read-write. this bit unconditionally goes to a 0b when the con gured bit in the ecap70 register makes a 0b to 1b transition. this bit unconditionally goes to 1b whenever the con gured bit is zero. system software uses this eld to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). software writes a one to this bit when the attached device is not a high-speed device. a one in this bit means that a companion host controller owns and controls the port. this bit resides in the aux power domain. 12 pp. port power . read-only. hardwired to 1b, since the host controller does not have port power control switches. each port is hardwired to power. 11:10 lstat. line status . read-only. these bits re ect the current logical levels of the d+ (bit 11) and d- (bit 10) signal lines. these bits are used for detection of low-speed usb devices prior to the port reset and enable sequence. this eld is valid only when the port enable bit is zero and the current connect status bit is set to a one. the encoding of the bits are: bits[11:10] usb state interpretation 00b se0 not low-speed device, perform ehci reset 10b j-state not low-speed device, perform ehci reset 01b k-state low-speed device, release ownership of port 11b unde ned not low-speed device, perform ehci reset. 9 reserved. hardwired to 0b. 8 pres. port reset . read-write. 1= port is in reset. 0= port is not in reset. when software writes a one to this bit (from a zero), the bus reset sequence as de ned in the usb speci cation revision 2.0 is started. software writes a zero to this bit to terminate the bus reset sequence. software must keep this bit at a one long enough to ensure the reset sequence, as speci ed in the usb speci cation revision 2.0, completes. note: when software writes this bit to a one, it must also write a zero to the port enable bit. note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero. the bit status does not read as a zero until after the reset has completed. if the port is in high- speed mode after reset is complete, the host controller automatically enables this port (e.g., sets the port enable bit to a one). a host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero. the hchalted bit in the ecap34 register should be a zero before software attempts to use this bit. the host controller may hold port reset asserted to a one when the hchalted bit is a one. this bit resides in the aux power domain. bits description chapter 4 registers 301 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 7 susp. suspend . read-write. 1= port in suspend state. 0= port not in suspend state. port enabled bit and suspend bit of this register de ne the port states as follows: bits [port enabled, suspend]port state 0x disable 10 enable 11 suspend when in suspend state, downstream propagation of data is blocked on this port, except for port reset. the blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. in the suspend state, the port is sensitive to resume detection. note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the usb. a write of zero to this bit is ignored by the host controller. the host controller unconditionally sets this bit to a zero when: software sets the force port resume bit to a zero (from a one). software sets the port reset bit to a one (from a zero). if host software sets this bit to a one when the port is not enabled (i.e., port enabled bit is a zero) the results are unde ned. this bit resides in the aux power domain. 6 fpr. force port resume . read-write. 1= resume detected/driven on port. 0= no resume (k-state) detected/driven on port. this functionality de ned for manipulating this bit depends on the value of the suspend bit. for example, if the port is not suspended (suspend and enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are unde ned. software sets this bit t oa1todrive resume signaling. the host controller sets this bit t oa1ifa j-to- k transition is detected while the port is in the suspend state. when this bit transitions to a one because a j-to-k transition is detected, the port change detect bit in the ecap34 register is also set to a one. if software sets this bit to a one, the host controller must not set the port change detect bit. note that when the ehci controller owns the port, the resume sequence follows the de ned sequence documented in the usb speci cation revision 2.0. the resume signaling (full-speed k ) is driven on the port as long as this bit remains a one. software must appropriately time the resume and set this bit to a zero when the appropriate amount of time has elapsed. writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle). this bit remains a one until the port has switched to the high-speed idle. the host controller must complete this transition within 2 milliseconds of software setting this bit to a zero. this bit resides in the aux power domain. 5 occ. over-current change . read; write 1 to clear. this bit gets set to a one when there is a change to over-current active. this bit resides in the aux power domain. 4 oca. over-current active . read-only. 1= this port currently has an over-current condition. 0= this port does not have an over- current condition. this bit automatically transitions from a one to a zero when the over current condition is removed. bits description 302 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 4.9.2.2.1 debug port registers these registers are located in memory-mapped io space. the base address register for these registers is dev0:2x14. 3 pec. port enable/disable change . read; write 1 to clear. 1= port enabled/disabled status has changed. for the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the eof2 point (see chapter 11 of the usb speci cation for the de nition of a port error). 2 pen. port enabled/disabled . read-write. 1= enable. 0= disable. ports can only be enabled by the host controller as a part of the reset and enable. software cannot enable a port by writing a one to this eld. the host controller only sets this bit to a one when the reset sequence determines that the attached device is a high-speed device. ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. note that the bit status does not change until the port state actually changes. there may be a delay in disabling or enabling a port due to other host controller and bus events. when the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset. this bit resides in the aux power domain. 1 csc. connect status change . read; write 1 to clear. 1= change in current connect status. 0= no change. indicates a change has occurred in the current connect status of the port. the host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. 0 ccs. current connect status . read-only. 1= device is present on port. 0= no device is present. default = 0. this value re ects the current state of the port, and may not correspond directly to the event that caused the connect status change bit to be set.this bit resides in the aux power domain. bits description chapter 4 registers 303 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information usb debug port control register dbg00 default: 0000_0000h. attribute: see below. bits description 31 reserved. hardwired to 0b. 30 own. owner . read-write. when debug software writes a one to this bit, the ownership of the debug port is forced to the ehci controller (i.e., immediately taken away from the companion controller). if the port was already owned by the ehci controller, then setting this bit is has no effect. this bit overrides all of the ownership related bits in the standard ehci registers. note that the value in this bit may not effect the value reported in the port owner bit in the associated ecap[88:74] register. 29 reserved. hardwired to 0b. 28 ena. enabled . read-write. this bit is a one if the debug port is enabled for operation. software can clear this by writing a zero to it. the controller clears the bit for the same conditions where hardware clears the port enable/disable change bit (in the ecap[88:74] register). (note: this bit is not cleared when system software clears the port enabled/disabled bit (in the ecap[88:74] register). software can directly set this bit, if the port is already enabled in the associated ecap[88:74] register (this is hw enforced). 27:17 reserved. hardwired to 000b. 16 done. done . read; write 1 to clear. this bit is set by hw to indicate that the request is complete. writing a 1 to this bit clears it. writing a 0 to this bit has no effect. 15:11 reserved. hardwired to 0h. 10 use. in use . read-write. set by software to indicate that the port is in use. cleared by software to indicate that the port is free and may be used by other software. (this bit has no affect on hardware.) 9:7 excp. exception . read-only. this eld indicates the exception when error/good_l is set. this eld cannot be cleared by software. value meaning 000b none 001b transaction error: indicates the usb2 transaction had an error (crc, bad pid, time-out, etc.) 010b hw error. request was attempted (or in progress) when port was suspended or reset. 011b-111b reserved 304 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 6 egd. error/good_l . read-only. updated by hardware at the same time it sets the done bit. when set it indicates that an error occurred. details of the error are provided in the exception eld. when cleared, it indicates that the request terminated successfully. 5 go. read-write. software sets this bit to cause the hardware to perform a request. writing this bit to a 1 when the bit is already set may result in unde ned behavior. writing a 0 to this bit has no effect. when set, the hardware clears this bit when the hardware sets the done bit. (completion of a request is indicated by the done bit.) 4 wrd. write-read_l . read-write. software sets this bit to indicate that the current request is a write and clears it to indicate a read. 3:0 dlen. data length . read-write. for write operations, this eld is set by software to indicate to the hardware how many bytes of data in data buffer are to be transferred to the console when write/read_l is set when software sets go. a value of 0h indicates that a zero-length packet should be sent. a value of 1 8 indicates 1 8 bytes are to be transferred. values 9 fh are illegal and how hardware behaves if used is unde ned. for read operations, this eld is set by hardware to indicate to software how many bytes in data buffer are valid in response to software setting go when write/read_l is cleared. a value of 0h indicates that a zero length packet was returned. (the state of data buffer is not de ned.) a value of 1 8 indicates 1 8 bytes were received. hardware is not allowed to return values 9 fh. the transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the transfer size is reached. bits description chapter 4 registers 305 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information usb debug port pids register dbg04 default: 0000_c3e1h. attribute: see below. usb debug port data buffer low dbg08 default: 0000_0000h. attribute: read-write. usb debug port data buffer high dbg0c default: 0000_0000h. attribute: read-write. data buffer must be written with data before software initiates a write request. for a read request, data buffer contains valid data when done is set, error/good_l is cleared, and data length speci?s the number of bytes that are valid. bits description 31:24 reserved. hardwired to 00h. 23:16 rpid. received pid . read-only. the debug port controller updates this eld with the received pid for transactions in either direction. when the controller is sending data (write/read_l is asserted), this eld is updated with the handshake pid that is received from the device. when the host controller is receiving data (write/ read_l is not asserted), this eld is updated with the data packet pid (if the device sent data), or the handshake pid (if the device naks the request). this eld is valid when the controller sets the done bit. 15:8 spid. send pid . read-write. the debug port controller sends this pid to begin the data packet when sending data to usb (i.e., write/read_l is asserted). software typically sets this eld to either data0 or data1 pid values. 7:0 tpid. token pid . read-write. the debug port controller sends this pid as the token pid for each usb transaction. software typically sets this eld to either in, out or setup pid values. bits description 31:0 dbl. data buffer low . first 4 bytes of data buffer. the least signi cant byte is accessed at offset 08h. each byte in data buffer can be individually accessed. bits description 31:0 dbh. data buffer high . second 4 bytes of data buffer.each byte in data buffer can be individually accessed. 306registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information usb debug port device address register dbg10 default: 0000_7f01h. attribute: see below. 4.10 lan ethernet controller registers 4.10.1 lan ethernet controller user accessible registers the network controller requires 4k bytes of memory address space for access to all the various internal registers. the network controller has three types of user accessible storage?he pci con?uration registers, the memory-mapped registers, and the internal rams. the internal rams include the mib counters, the pattern match ram, and the autopoll value ram. user access to these memories is indirect with a protocol similar to the external phy access protocol. associated with each of these memories is an xxx_addr and an xxx_data register, where xxx stands for mib, pmr, or ap_val. the xxx_addr register contains the address of the memory element to be accessed plus a wr_cmd bit, a rd_cmd bit, and a cmd_active bit. the cmd_active bit is a read-only bit that is automatically set when the wr_cmd or rd_cmd bit is set and is automatically cleared when the operation is complete. the procedure for writing to one of these internal memories is: 1. poll the appropriate cmd_active bit until this bit is 0. 2. write the data into xxx_data. 3. write the address of the element to be accessed to xxx_addr, with the wr_cmd bit set. the procedure for reading from one of these internal memories is: 1. poll the appropriate cmd_active bit until this bit is 0. 2. write the address of the element to be accessed to xxx_addr, with the rd_cmd bit set. 3. poll the appropriate cmd_active bit until this bit is 0. bits description 31:15 reserved. hardwired to 00000h. 14:8 uadr. usb address . read-write. 7-bit eld that identi es the usb device address used by the controller for all token pid generation. 7:4 reserved. hardwired to 0h. 3:0 uep. usb endpoint . read-write. 4-bit eld that identi es the endpoint used by the controller for all token pid generation. chapter 4 registers 307 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 4. read the data from xxx_data. the pci con?uration registers and the memory-mapped registers can be accessed in any data width up to 32 bits. the controller's registers can be divided into several functional groups: pci con?uration alias registers, pci con?uration registers, setup registers, running registers, and test registers. the pci con?uration alias registers are typically programmed by the chip set initialization software. in this way, they are initialized before the bios accesses the pci con?uration registers. this group includes the vendor id alias, device id alias, sub vendor id alias, sub system id alias, min_gnt alias, max_lat alias, and pmc alias registers at offsets c0h to dfh in pci con?uration space. the pci con?uration registers are accessed by the system bios software to con?ure the network controller. these registers include the memory base address register, the interrupt line register, the pci command register, the pci status register and the pmc register. typically, device information is also read from the sid, svid and vid registers. the setup registers include most of the remaining memory-mapped registers. the programming of these is typically divided between the chip set initialization software and the driver software. many of these registers are optional and need not be initialized unless the associated function is used. typically, the sram_size, sram_bnd and padr registers are initialized by the chip set initialization software. the driver initializes the badr, badx, rcv_ring_len, xmt_ring_len and ladrf registers. the cmd2, cmd3, ctrl1 and ctrl2 registers are typically partially initialized by the chip set initialization software and partially by the driver. the cmd7 register is initialized by the driver. the driver reads the chipid register at initialization time. the phy_access register may be used at this time to initialize the external phy. running registers are accessed by the driver software. these include the cmd0, int0, inten0, stat0, ladrf and mib registers. the driver may access other registers during operation depending on the features being used. 308 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 4.10.2 lan ethernet controller con guration registers (dev1:0xxx) lan ethernet controller vendor and device id dev1:0x00 default: 7462_1022h attribute: read-only lan ethernet controller command and status dev1:0x04 default: 0210_0000h attribute: see below ?ld. lan ethernet controllerrevision id and class code dev1:0x08 default: 0200_00xxh see below. attribute: read-only lan ethernet controller bist, header and latency dev1:0x0c default: 0000_0010h attribute: see below. bits description 31:16 encid. provides the lan ethernet controller device identi cation . 15:0 amdid. provides amd s pci vendor identi cation . bits description 31:16 stat. read-only. 15:0 cmd. cmd[15:3]: read-only. cmd[2]: bmen . bus master enable . read-write. 1 = enables bus master capability. the host must set bmen before setting the run bit in cmd0 of the ethernet controller. 0 = disables bus master capability. bmen is reset by h_reset. cmd[1]: memen . memory space enable . read-write. 1 = access to memory space for this device is enabled. 0 = access to memory space for this device is disabled. memen is reset by h_reset. cmd[0]: reserved. bits description 31:24 baseclass. these bits are xed at 02h indicating a network controller. 23:16 subclass . these bits are xed at 00h indicating an ethernet controller. 15:8 progif . 7:0 revid. lan ethernet controller silicon revision . the value of this register is revision-dependent. bits description chapter 4 registers 309 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller command interface base address dev1:0x10 default: 0000_0000h attribute: see below. lan ethernet controller subsystem and subsystem vendor id dev1:0x2c default: 0000_0000h attribute: read only. note: this register is aliased to dev1:0xc8 for modi?ations. 31:24 bist. read-only. 23:16 header . read-only. 15:8 latency. read-write. the latency timer de nes the minimum amount of time, in pci clock cycles, that the bus master can retain ownership of the bus. the two least signi cant bits are xed to 0b. 7:0 read-only. bits description 31:12 membase. memory-mapped register base address . read-write. these bits are used in the memory space decode of the memory-mapped registers. there is a maximum block size of 4k bytes for this base address. this register is reset by h_reset. 11:1 read-only. 0 rte. resource type indicator . this bit is xed to 0b, indicating memory address space. bits description 31:16 subsysid. subsystem id . 15:0 subvenid. subsystem vendor id . 310 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller capabilities pointer dev1:0x34 default: 40h attribute: read only. lan ethernet controller interrupt line and interrupt pin dev1:0x3c default: 0100h attribute: see below. lan ethernet controller min grant and max latency dev1:0x3e default: 0000_0000h attribute: read only. note: this register is aliased to dev1:0xce for modi?ations. bits description 7:0 capptr. capabilities pointer . bits description 15:11 reserved 10:8 intpin. read-only. indicates which pci interrupt pin is used for the lan ethernet controller interrupt. hardwired to 001b to select pirqa_l. 7:0 intline. read-write. this data is not used by hardware. it is used to communicate across software the interrupt line that the interrupt pin is connected to. this register is reset by h_reset. bits description 15:8 maxlat. maximum latency . this register speci es the maximum arbitration latency the controller can sustain without causing problems to the network activity. the register value speci es the time in units of 1/4 s. it is recommended that the alias register be programmed to a value of 18h, which corresponds to 6 s. 7:0 mingnt. minimum grant . this register speci es the minimum length of a burst period that the device needs to keep up with the network activity. the length of the burst period is calculated assuming a clock rate of 33 mhz. the register value speci es the time in units of 1/4 s. it is recommended that the alias register be programmed to a value of 18h, which corresponds to 6 s. chapter 4 registers 311 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller power management capabilities dev1:0x40 default: fe02_0001h attribute: read only. lan ethernet controller power management control and status dev1:0x44 default: 0000h attribute: see below. lan ethernet controller subsystem and subsystem vendor id alias dev1:0xc8 bits description 31:16 pmc. power management capabilities . 15:8 ncptr. next capability pointer . 7:0 pmcid. power management capability id . bits description 15 pmests. pme status . read, write 1b to clear. this bit is set when the function would normally assert the pme signal independent of the state of the pme_en bit. writing 1b to this bit clears it and causes the function to stop asserting the pme_l signal (if enabled). writing a 0 has no effect. if the function supports pme from d3cold then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. this bit is reset by por. if the function does not support pme signal assertion from d3cold, either because bit 15 of the pmc alias register is 0b or devb:3x64[l7_s3en] is 0b, pme_status is reset following h_reset. 14:9 reserved. 8 pmeen. pme enable . read-write. when 1b, pme_en enables the function to assert the pme_l signal. when 0b, pme assertion is disabled. this bit defaults to 0b if the function does not support pme_l signal generation from d3cold. if the function supports pme_l signal generation from d3cold, then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. this bit is reset by por. if the function does not support pme_l signal assertion from d3cold, either because bit 15 of the pmc alias register is 0b or devb:3x64[l7_s3en] is 0b, pme_status is reset following h_reset. 7:2 reserved. 1:0 pwrstat. power state . read-write. this 2-bit eld is used both to determine the current power state of a function and to set the function into a new power state. the de nition of the eld values is as follows: 00b d0 01b d1 10b d2 11b d3 these bits can be written and read, but their contents have no effect on the operation of the device, except that when power state is not 0, the device only responds to pci con guration space accesses, and when power state transitions from 3 to 0, the read-write bits of the pci con guration space are reset. this reset does not clear pme_en or pme_status and also does not change read-only bits initialized by the bios. 312 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information default: 0000_0000h attribute: read/write note: this register is aliased to dev1:0x2c for modi?ations. lan ethernet controller min grant and max latency alias dev1:0xce default: 0000h attribute: read/write note: this register is aliased to dev1:0x3e for modi?ations. 4.10.3 memory-mapped registers the memory-mapped registers give the host cpu access to all programmable features of the device. these registers are mapped directly into pci memory space so that any programmable feature can be accessed with a single pci memory read or write transaction. data in these registers can be accessed as a single byte, a 16-bit word, or a 32-bit double word. registers that are logically wider than a double word are shown in the register descriptions as a single register. these may be accessed using multiple smaller accesses or with a single burst access. some registers that are smaller than a double word in width (stval, padr[47:32], xmt_ring_len, rcv_ring_len) are placed in the memory map in the lower half of a double word. the upper half ignores writes and reads back zeros (stval, padr[47:32]) or ones (xmt_ring_len, rcv_ring_len) as appropriate for sign extension. this allows these registers to be accessed with double word reads and writes. 4.10.3.1 command style register access the command and interrupt enable registers (cmd0, cmd2, cmd3, cmd7, and inten0) use a write access technique that in this document is called command style access. command style access allows the host cpu to write to selected bits of a register without altering bits that are not selected. command style registers are divided into 4 bytes that can be written independently. the high order bit of each byte is the ?alue bit that speci?s the value that is written to selected bits of the register. the 7 low order bits of each byte make up a bit map that selects which register bits are altered. if a bit in the bit map is set to 1, the corresponding bit in the register is loaded with the contents of the value bit. if a bit in the bit map is cleared to 0, the corresponding bit in the register is not altered. bits description 31:16 subsysid. subsystem id . 15:0 subvenid. subsystem vendor id . bits description 15:8 maxlat. maximum latency . 7:0 mingnt. minimum grant . chapter 4 registers 313 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information for example, if the value 10011010b is written to the least signi?ant byte of a command style register, bits 1, 3, and 4 of the register are set to 1, and the other bits are not altered. if the value 00011010b is written to the same byte, bits 1, 3, and 4 are cleared to 0, and the other bits are not altered. in the worst case it takes two write accesses to write to all of the bits in a command style register. one access writes to all bits that should be set to 1, and the other access writes to all bits that should be cleared to 0. 4.10.3.2 memory-mapped register descriptions in the following register descriptions, the offset listed for each register is the offset relative to the contents of the pci memory-mapped i/o base address register. in addition to the usual register tables the descriptions below include a write mode identi?r with the following meaning: write mode description r the register can be written any time. (can be written while the device is running.) n the register can be written only when the device is not running (when run=0). sn the register can be written when the device is suspended or not running. 1 the register can be written only when en_pmgr and apep are both 0. 2 the register can be written only when reset_phy_pulse is 0. 3 the register can be written only when pmat_mode is 0. 314 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller auto-poll value enc98 default: 0000_0000h attribute: see below. this register provides indirect access to registers in the physical layer device. the access protocol is: 1. read ap_value until ap_val_active is 0. 2. write ap_value with ap_val_rd_cmd = 1 and ap_val_addr set to the address of the desired autopoll value register (0?). 3. read ap_value until ap_val_active is 0. the autopoll value is in the ap_val ?ld. this register is reset by h_reset. bits description 31 ap_val_active. autopoll value active . read-only. this bit is set to 1 while the contents of the selected autopoll data register are being fetched. when this bit is 1, the ap_val eld of this register does not contain valid data. the host cpu must wait until this bit is 0 before it can write to this register. 30 reserved. 29 ap_val_rd_cmd. autopoll read command . write-only; write mode r. writing 1 to this bit starts a read access cycle the contents of the autopoll data register addressed by the ap_val_addr eld of this register are loaded into the ap_val eld of this register. writing a 0 to this bit has no effect. 28 ap_rd_err. autopoll read error . read-only. this bit is automatically set to 1 if a read error occurred when the selected auto-poll data register was last read. if this bit is 1, the contents of the ap_val eld are not valid. 27:19 reserved. 18:16 ap_val_addr. autopoll data register address . read-write; write mode r. this eld contains the address of the autopoll data register (0-5) whose value is loaded into the ap_val eld of this register during a read cycle. 15:0 ap_val. autopoll data register value . read-only. this eld shows the contents of the selected external autopoll data register register. chapter 4 registers 315 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller auto-poll 0 enc88 default: 8100h attribute: read-only. this register controls the automatic polling of the status register of the default external phy. this register is reset by h_reset. lan ethernet controller auto-poll 1 enc8a default: 0000h attribute: read-write; write mode 1. this register controls the automatic polling of a user-selectable external phy register. bits description 15 ap_reg0_en. enable bit for autopoll register 0 . this bit is read-only and always has the value 1. 14:13 reserved. 12:8 ap_reg0_addr. ap_reg0 address . this eld is read-only and always has the value 00001. 7:3 reserved. 4:0 ap_phy0_addr. auto-poll phy0 address . this eld contains the address of the external phy that contains ap-reg0. the network port manager uses this phy address for auto-negotiation. the autopoll state machine also uses this eld as the default phy address when one or more of the ap_phyn_dflt bits are set. bits description 15 ap_reg1_en. enable bit for autopoll register 1 . when this bit and the auto-poll external phy bit (apep) in cmd3 are both set to 1, the auto-poll state machine periodically reads the external phy register selected by the ap_phy1_addr and ap_reg1_addr elds and sets the apint1 interrupt bit if it detects a change in the register s contents. 14:13 reserved. 12:8 ap_reg1_addr. ap_reg1 address . this eld contains the register number of an external phy register that the auto-poll state machine periodically reads if the ap_reg1_en bit in this register and the apep bit (cmd3, bit 10) are set. 7 reserved. 6 ap_pre_sup1. auto-poll preamble suppression . if this bit is set to 1, the auto-poll state machine suppresses the preambles of the mii management frames that it uses to periodically read the external phy register selected by the ap_phy1_addr and ap_reg1_addr elds. this bit is ignored when the ap_phy1_dflt bit is set. 5 ap_phy1_dflt. auto-poll phy1 default . when this bit is set, the auto-poll state machine ignores the contents of the ap_phy1_addr and ap_pre_sup1 elds and uses the ap_phy0_addr eld for the address of the phy device to be polled. if this bit is set, the auto-poll state machine suppresses preambles only if the port manager has determined that the default external phy can accept mii management frames without preambles. (the port manager examines bit 6 in register 1 of the default phy to make this determination.) 4:0 ap_phy1_addr. auto-poll phy1 address . this eld contains the address of the external phy that contains ap_reg1. this bit is ignored when the ap_phy1_dflt bit is set. 316registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information this register is reset by h_reset. lan ethernet controller auto-poll 2 enc8c default: 0000h attribute: read-write; write mode 1. this register controls the automatic polling of a user-selectable external phy register, ap_reg2. this register is reset by h_reset. bits description 15 ap_reg2_en. enable bit for autopoll register 2 . when this bit and the auto-poll external phy bit (apep) in cmd3 are both set to 1, the auto-poll state machine periodically reads the external phy register selected by the ap_phy2_addr and ap_reg2_addr elds and sets the apint2 interrupt bit if it detects a change in the register s contents. 14:13 reserved. 12:8 ap_reg2_addr. ap_reg2 address . this eld contains the register number of an external phy register that the auto-poll state machine periodically reads if the ap_reg2_en bit in this register and the apep bit (cmd3, bit 10) are set. 7 reserved. 6 ap_pre_sup2. auto-poll preamble suppression . if this bit is set to 1, the auto-poll state machine suppresses the preambles of the mii management frames that it uses to periodically read the external phy register selected by the ap_phy2_addr and ap_reg2_addr elds.this bit is ignored when the ap_phy2_dflt bit is set. 5 ap_phy2_dflt. auto-poll phy2 default . when this bit is set, the auto-poll state machine ignores the contents of the ap_phy2_addr and ap_pre_sup2 elds and uses the ap_phy0_addr eld for the address of the phy device to be polled. if this bit is set, the auto-poll state machine suppresses preambles only if the port manager has determined that the default external phy can accept mii management frames without preambles. (the port manager examines bit 6 in register 1 of the default phy to make this determination.) 4:0 ap_phy2_addr. auto-poll phy2 address . this eld contains the address of the external phy that contains ap_reg2.this bit is ignored when the ap_phy2_dflt bit is set. chapter 4 registers 317 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller auto-poll 3 enc8e default: 0000h attribute: read-write; write mode 1. this register controls the automatic polling of a user-selectable external phy register, ap_reg3. this register is reset by h_reset. bits description 15 ap_reg3_en. enable bit for autopoll register 3 . when this bit and the auto-poll external phy bit (apep) in cmd3 are both set to 1, the auto-poll state machine periodically reads the external phy register selected by the ap_phy3_addr and ap_reg3_addr elds and sets the apint3 interrupt bit if it detects a change in the register s contents. 14:13 reserved. 12:8 ap_reg3_addr. ap_reg3 address . this eld contains the register number of an external phy register that the auto-poll state machine periodically reads if the ap_reg3_en bit in this register and the apep bit (cmd3, bit 10) are set. 7 reserved. 6 ap_pre_sup3. auto-poll preamble suppression . if this bit is set to 1, the auto-poll state machine suppresses the preambles of the mii management frames that it uses to periodically read the external phy register selected by the ap_phy3_addr and ap_reg3_addr elds. this bit is ignored when the ap_phy3_dflt bit is set. 5 ap_phy3_dflt. auto-poll phy3 default . when this bit is set, the auto-poll state machine ignores the contents of the ap_phy3_addr and ap_pre_sup3 elds and uses the ap_phy0_addr eld for the address of the phy device to be polled. if this bit is set, the auto-poll state machine suppresses preambles only if the port manager has determined that the default external phy can accept mii management frames without preambles. (the port manager examines bit 6 in register 1 of the default phy to make this determination.) 4:0 ap_phy3_addr. auto-poll phy3 address . this eld contains the address of the external phy that contains ap_reg3. this bit is ignored when the ap_phy3_dflt bit is set. 318 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller auto-poll 5 enc90 default: 0000h attribute: read-write; write mode 1. this register controls the automatic polling of a user-selectable external phy register, ap_reg4. this register is reset by h_reset. bits description 15 ap_reg4_en. enable bit for autopoll register 4 . when this bit and the auto-poll external phy bit (apep) in cmd3 are both set to 1, the auto-poll state machine periodically reads the external phy register selected by the ap_phy4_addr and ap_reg4_addr elds and sets the apint4 interrupt bit if it detects a change in the register s contents. 14:13 reserved. 12:8 ap_reg4_addr. ap_reg4 address . this eld contains the register number of an external phy register that the auto-poll state machine periodically reads if the ap_reg4_en bit in this register and the apep bit (cmd3, bit 10) are set. 7 reserved. 6 ap_pre_sup4. auto-poll preamble suppression . if this bit is set to 1, the auto-poll state machine suppresses the preambles of the mii management frames that it uses to periodically read the external phy register selected by the ap_phy4_addr and ap_reg4_addr elds. this bit is ignored when the ap_phy4_dflt bit is set. 5 ap_phy4_dflt. auto-poll phy4 default . when this bit is set, the auto-poll state machine ignores the contents of the ap_phy4_addr and ap_pre_sup4 elds and uses the ap_phy0_addr eld for the address of the phy device to be polled. if this bit is set, the auto-poll state machine suppresses preambles only if the port manager has determined that the default external phy can accept mii management frames without preambles. (the port manager examines bit 6 in register 1 of the default phy to make this determination.) 4:0 ap_phy4_addr. auto-poll phy4 address . this eld contains the address of the external phy that contains ap_reg4. this bit is ignored when the ap_phy4_dflt bit is set. chapter 4 registers 319 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller auto-poll 5 enc92 default: 0000h attribute: read-write; write mode 1. this register controls the automatic polling of a user-selectable external phy register, ap_reg5. this register is reset by h_reset. lan ethernet controller receive ring base address enc120 default: 0000_0000h attribute: read-write. this 32-bit register allows the receive descriptor ring to be located anywhere in a 32-bit address space. this register is reset by reset_l. bits description 15 ap_reg5_en. enable bit for autopoll register 5 . when this bit and the auto-poll external phy bit (apep) in cmd3 are both set to 1, the auto-poll state machine periodically reads the external phy register selected by the ap_phy5_addr and ap_reg5_addr elds and sets the apint5 interrupt bit if it detects a change in the register s contents. 14:13 reserved 12:8 ap_reg5_addr. ap_reg5 address . this eld contains the register number of an external phy register that the auto-poll state machine periodically reads if the ap_reg5_en bit in this register and the apep bit (cmd3, bit 10) are set. 7 reserved. 6 ap_pre_sup5. auto-poll preamble suppression . if this bit is set to 1, the auto-poll state machine suppresses the preambles of the mii management frames that it uses to periodically read the external phy register selected by the ap_phy5_addr and ap_reg5_addr elds.this bit is ignored when the ap_phy5_dflt bit is set. 5 ap_phy5_dflt. auto-poll phy5 default . when this bit is set, the auto-poll state machine ignores the contents of the ap_phy5_addr and ap_pre_sup5 elds and uses the ap_phy0_addr eld for the address of the phy device to be polled. if this bit is set, the auto-poll state machine suppresses preambles only if the port manager has determined that the default external phy can accept mii management frames without preambles. (the port manager examines bit 6 in register 1 of the default phy to make this determination.) 4:0 ap_phy5_addr. auto-poll phy5 address . this eld contains the address of the external phy that contains ap_reg5.this bit is ignored when the ap_phy5_dflt bit is set. bits description 31:0 badr. base address of receive descriptor ring . 320 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller transmit ring 0 base address enc100 default: 0000_0000h attribute: read-write. this 32-bit register allows the transmit descriptor rings to be located anywhere in a 32-bit address space. this register is reset by reset_l. lan ethernet controller transmit ring 1 base address enc108 default: 0000_0000h attribute: read-write. this 32-bit register allows the transmit descriptor rings to be located anywhere in a 32-bit address space. this register is reset by reset_l. lan ethernet controller transmit ring 2 base address enc110 default: 0000_0000h attribute: read-writeread-write. this 32-bit register allows the transmit descriptor rings to be located anywhere in a 32-bit address space. this register is reset by reset_l. lan ethernet controller transmit ring 3 base address enc118 default: 0000_0000h attribute: read-write. this 32-bit register allows the transmit descriptor rings to be located anywhere in a 32-bit address space. this register is reset by reset_l. bits description 31:0 badx0. base address of transmit descriptor ring 0 . bits description 31:0 badx1. base address of transmit descriptor ring 1 . bits description 31:0 badx2. base address of transmit descriptor ring 2 . bits description 31:0 badx3. base address of transmit descriptor ring 3 . chapter 4 registers 321 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller chip id enc004 default: ????_?003h attribute: read-only. this register holds a product identi?ation number that system software can use to determine which software driver to load. note that the part number & manufacturer id are not the same as the values in the pci con?uration space. bits description 31:28 ver. version . this 4-bit pattern is silicon-revision dependent. 27:12 partid. part number . the 16-bit codes for the controller are unde ned at present. this part number is different from that stored in the device id register in the pci con guration space. 11:1 manfid. manufacturer id . the 11-bit manufacturer code for amd is 00000000001b. this code is per the jedec publication 106-a. note that this code is not the same as the vendor id in the pci con guration space. 0 one. always 1 . 322 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller command 0 (cmd0) enc048 default: 0000_0000h attribute: see below. bits description 31 valbit3 . value bit for byte 3 . read-write. the value of this bit is written to any bits in the cmd0 register that correspond to bits in the cmd0[30:24] bit map eld that are set to 1. 30:24 reserved. 23 valbit2 . value bit for byte 2 . read-write. the value of this bit is written to any bits in the cmd0 register that correspond to bits in the cmd0[22:16] bit map eld that are set to 1. 22:17 reserved. 16 rdmd0. receive demand for ring 0 . write-only; write mode r. when set causes the descriptor management unit to access the receive descriptor ring if it does not already own the next descriptor. this bit is also reset when the run bit is cleared. 15 valbit1 . value bit for byte 1 . read-write. the value of this bit is written to any bits in the cmd0 register that correspond to bits in the cmd0[14:8] bit map eld that are set to 1. 14:12 reserved. 11 tdmd3. transmit demand for ring 3 . write-only; write mode r. which when set causes the buffer management unit to access the transmit descriptor ring. this bit is also reset when the run bit is cleared. 10 tdmd2. transmit demand for ring 2 . write-only; write mode r. which when set causes the buffer management unit to access the transmit descriptor ring. this bit is also reset when the run bit is cleared. 9 tdmd1. transmit demand for ring 1 . write-only; write mode r. which when set causes the buffer management unit to access the transmit descriptor ring. this bit is also reset when the run bit is cleared. 8 tdmd0. transmit demand for ring 0 . write-only; write mode r. which when set causes the buffer management unit to access the transmit descriptor ring. this bit is also reset when the run bit is cleared. 7 valbit0 . value bit for byte 1 . read-write. the value of this bit is written to any bits in the cmd0 register that correspond to bits in the cmd0[6:0] bit map eld that are set to 1. 6 uintcmd. user interrupt command . write-only; write mode r. uintcmd can be used by the host to generate an interrupt unrelated to any network activity. writing a 1 to this bit causes the uint bit in the interrupt register to be set to 1, which in turn causes inta to be asserted if interrupts are enabled. this bit is also reset when the run bit is cleared. 5 rx_fast_spnd. receive fast suspend . read-write; write mode r. setting this bit causes the receiver to suspend its activities as quickly as possible without stopping in the middle of a frame reception. setting rx_fast_spnd does not stop the dma controller from transferring frame data from the receive fifo to host memory. if a frame is being received at the time that rx_fast_spnd is set to 1, the reception of that frame is completed, but no more frames are received until rx_fast_spnd is cleared to 0. after the receiver has suspended its activity, the rx_suspended bit in the status register and the suspend interrupt (spndint) bit in the interrupt register are set, which causes an interrupt to occur if interrupts are enabled and the spndinten bit in the interrupt enable register is set. this bit is also reset when the run bit is cleared. chapter 4 registers 323 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information cmd0 is a command-style register. this register is reset by reset_l. some bits in this register are also reset when the run bit is cleared. 4 tx_fast_spnd. transmit fast suspend . read-write; write mode r. setting this bit causes the transmitter to suspend its activities as quickly as possible without stopping in the middle of a frame transmission. setting tx_fast_spnd does not stop the dma controller from transferring frame data from host memory to the transmit fifo. if a frame is being transmitted at the time that tx_fast_spnd is set to 1, the transmission of that frame is completed, but no more frames are transmitted until tx_fast_spnd is cleared to 0. after the transmitter has suspended its activity, the tx_suspended bit in the status register and the suspend interrupt (spndint) bit in the int0 register are set, which causes an interrupt to occur if interrupts are enabled and the spndinten bit in the interrupt enable register is set. this bit is also reset when the run bit is cleared. 3 rx_spnd. receive suspend . read-write; write mode r. setting this bit causes the receiver to suspend its activities without stopping in the middle of a frame reception. after the receiver suspends its activities, the dma controller continues copying data from the receive fifo into host system memory until the fifo is empty. after the receive fifo has been emptied, the rx_suspended bit in the status register and the suspend interrupt (spndint) bit in the interrupt register are set. setting the spndint bit causes an interrupt to occur if interrupts are enabled and the spndinten bit in the interrupt enable register is set. this bit is also reset when the run bit is cleared. 2 tx_spnd. transmit suspend . read-write; write mode r. setting this bit causes the transmitter to suspend its activities without stopping in the middle of a frame transmission. the dma controller suspends after completing the copying of data from host system memory into the transmit fifo for the current frame (if any). the transmitter continues operation until all frames in the transmit fifo have been transmitted. the tx_suspended bit in the status register and the suspend interrupt (spndint) bit in the interrupt register are then set. setting the spndint bit causes an interrupt to occur if interrupts are enabled and the spndinten bit in the interrupt enable register is set. this bit is also reset when the run bit is cleared. 1 intren. interrupt enable . read-write; write mode r. this bit allows inta to be asserted if any bit in the interrupt register is set. if intren is cleared to 0, inta is not asserted, regardless of the state of the interrupt register. 0 run. run bit . read-write; write mode r. setting the run bit enables the controller to start processing descriptors and transmitting and receiving packets. clearing the run bit to 0 abruptly disables the transmitter, receiver, and descriptor processing logic, possibly while a frame is being transmitted or received. the act of changing the run bit from 1 to 0 causes the following bits to be reset to 0: tx_spnd, rx_spnd, tx_fast_spnd, rx_fast_spnd, rdmd, all tdmd bits, rint, all tint bits, mpint, and spndint. bits description 324 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller command 2 (cmd2) enc050 default: 0000_0000h attribute: read-write; write mode n. bits description 31 valbit3 . value bit for byte 3 . read-write. the value of this bit is written to any bits in the cmd2 register that correspond to bits in the cmd2[30:24] bit map eld that are set to 1. 30 reserved. 29 conduit_mode. disables backoff and retry . transmit retry and frame discard is controlled by col and crs. see conduit mode section for details. 28:24 reserved. 23 valbit2 . value bit for byte 2 . read-write. the value of this bit is written to any bits in the cmd2 register that correspond to bits in the cmd2[22:16] bit map eld that are set to 1. 22:20 reserved. 19 rpa. runt packet accept . this bit forces the controller to accept runt packets (packets shorter than 64 bytes). the minimum packet size that can be received is 12 bytes including the fcs. 18 drcvpa. disable receive physical address . when set, the physical address detection (station or node id) of the controller is disabled. frames addressed to the node s individual physical address will not be recognized. 17 drcvbc. disable receive broadcast . when set, disables the controller from receiving broadcast messages. used for protocols that do not support broadcast addressing, except as a function of multicast. drcvbc is cleared by activation of h_reset (broadcast messages will be received) and is unaffected by the clearing of the run bit. 16 prom. promiscuous mode . when prom = 1, all incoming receive frames are accepted, regardless of their destination addresses. 15 valbit1 . value bit for byte 1 . read-write. the value of this bit is written to any bits in the cmd2 register that correspond to bits in the cmd2[14:8] bit map eld that are set to 1. 14 reserved. 13 astrip_rcv. auto strip receive . when set, astrip_rcv enables the automatic pad stripping feature. for any receive frame whose length eld has a value less than 46, the pad and fcs elds are stripped and not placed in the fifo. 12 rcv_drop0. if this bit is set, receive frames assigned to ring 0 are dropped if no descriptor is available when the frame is ready to be written to system memory. if the bit is 0, these frames are saved until descriptors are available. 11 emba. enable modi ed back-off algorithm (see contention resolution section in media access management section for more details). if emba is set, a modi ed back-off algorithm is implemented. 10 dxmt2pd. disable transmit two part deferral (see medium allocation section in the media access management section for more details). if dxmt2pd is set, transmit two part deferral is disabled. 9 ltinten. last transmit interrupt enable . when this bit is set to 1, the ltint bit in transmit descriptors can be used to determine when transmit interrupts occur. the transmit interrupt (tint) bit is set after a frame has been copied to the transmit fifo if the ltint bit in the frame s last transmit descriptor is set. if the ltint bit in the frame s last descriptor is 0, tint is not set after the frame has been copied to the transmit fifo. chapter 4 registers 325 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information cmd2 is a command-style register. this register is reset by reset_l. 8 dxmtfcs. disable transmit crc (fcs) . when dxmtfcs is cleared to 0, the transmitter generates and appends an fcs to the transmitted frame. when dxmtfcs is set to 1, no fcs is generated or sent with the transmitted frame. dxmtfcs is overridden when add_fcs and enp bits are set in the transmit descriptor. when the auto padding logic, which is enabled by the apad_xmt bit (cmd2, bit6), adds padding to a frame, a valid fcs eld is appended to the frame, regardless of the state of dxmtfcs. if dxmtfcs is set and add_fcs is clear for a particular frame, no fcs is generated. if add_fcs is set for a particular frame, the state of dxmtfcs is ignored and a fcs is appended on that frame by the transmit circuitry. see also the add_fcs bit in the transmit descriptor. this bit was called dtcr in the am7990 device. 7 valbit0 . value bit for byte 1 . read-write. the value of this bit is written to any bits in the cmd2 register that correspond to bits in the cmd2[6:0] bit map eld that are set to 1. 6 apad_xmt. auto pad transmit . when set, apad_xmt enables the automatic padding feature. transmit frames are padded to extend them to 64 bytes including fcs. the fcs is calculated for the entire frame, including pad, and appended after the pad eld. when the auto padding logic modi es a frame, a valid fcs eld is appended to the frame, regardless of the state of the dxmtfcs bit (cmd2, bit 8) and of the add_fcs bit in the transmit descriptor. 5 drty. disable retry . when drty is set to 1, the controller attempts only one transmission. in this mode, the device does not protect the rst 64 bytes of frame data in the transmit fifo from being overwritten, because automatic retransmission will not be necessary. when drty is cleared to 0, the controller attempts 16 transmissions before signaling a retry error. 4 inloop. internal loopback . when this bit is set, the transmitter is internally connected to the receiver so that the data output and control signals are connected internally to the data input and control signals. the device is forced into full duplex mode so that collisions can not occur. the inloop and exloop bits should not be set at the same time. 3 exloop. external loopback . when this bit is set, the device is forced into full duplex mode so that collisions can not occur during loop back testing. if the phy interface output signals are connected externally to the phy interface inputs, then transmitted frames will also be received. this connection can be made by attaching an external jumper or by programming an attached phy to loopback mode. the inloop and exloop bits should not be set at the same time. 2 reserved. 1 rex_uflo. retransmit on under ow . when this bit is set to 1, if the transmitter is forced to abort a transmission because the transmit fifo under ows, the transmitter does not discard the frame. instead, it automatically waits until the entire frame has been loaded into the transmit fifo and then restarts the transmission process. when this bit is cleared to 0, if the transmitter is forced to abort a transmission because the fifo under ows, the transmitter discards the frame. in either case, the xmtunderrunpkts counter is incremented. 0 reserved. bits description 326registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller command 3 (cmd3) enc054 default: 0000_0000h attribute: see below. bits description 31 valbit3 . value bit for byte 3 . read-write. the value of this bit is written to any bits in the cmd3 register that correspond to bits in the cmd3[30:24] bit map eld that are set to 1. 30:29 reserved. 28:24 reserved. 23 valbit2 . value bit for byte 2 . read-write. the value of this bit is written to any bits in the cmd3 register that correspond to bits in the cmd3[22:16] bit map eld that are set to 1. 21 jumbo. write mode n. accept jumbo frames . read-write. this bit affects the way the mib counters count long frames. if jumbo is 0, only frames that are between 64 and 1518 bytes (or 1522 bytes if vsize is set to 1) are counted as valid frames. when jumbo is 1, any frame between 64 and 9018 bytes (or 9022 bytes if vsize is set to 1) with a valid fcs eld is counted as a valid frame. 20 vsize. write mode n. vlan frame size . read-write. this bit determines the maximum frame size used for determining when to increment the xmtpkts1024to1518octets, xmtexcessivedefer, rcvpkts1024to1518octets, and rcvoversizepkts mib counters and when to assert the excessive deferral interrupt. when this bit is set to 1 the maximum frame size is 1522 bytes (or 9022 if jumbo is set). when it is cleared to 0, the maximum frame size is 1518 bytes (or 9018 if jumbo is set). 19 vlonly. write mode n. admit only vlan frames . read-write. when this bit is set to 1, only frames with a vlan tag header containing a non-zero vlan id eld are received. all other frames are rejected. 18 vl_tag_del. write mode n. delete vlan tag . read-write. if this bit is set, the receiver deletes the 4 bytes of vlan tag from the frame data. the vlan tag information is reported in the descriptor. the number of bytes written to system memory and the mcnt eld of the receive descriptor is 4 smaller than the actual number of bytes received. the mib counters are incremented by the actual number of bytes received. 17:16 reserved. 15 valbit1 . value bit for byte 1 . read-write. the value of this bit is written to any bits in the cmd3 register that correspond to bits in the cmd3[14:8] bit map eld that are set to 1. 14 en_pmgr. write mode n. enables the port manager . read-write. en_pmgr is cleared on reset, so the port manager starts only after bios is complete. this bit is the inverse of bits called danas or dispm in certain other amd network controllers. 13 reserved. 12 force_full_duplex. write mode n. force full duplex . read-write. this bit is called full- duplex enable (fden) in other pcnet family devices.) this bit controls whether full-duplex operation is enabled. when force_fd is cleared and the port manager is disabled, the controller will always operate in the half-duplex mode. when force_fd is set, the controller operates in full- duplex mode. do not set this bit when the port manager is enabled. 11 force_link_status. write mode n. force link status . read-write. when this bit is set, the internal link status is forced to the pass state regardless of the actual state of the phy device. when this bit is cleared to 0, the internal link status is determined by the port manager. 10 apep. write mode r. mii auto-poll external phy (apep). read-write. when set to 1, the network controller polls the mii status register in the external phy. this feature allows the software driver or upper layers to see any changes in the status of the external phy. an interrupt, when enabled, is generated when the contents of the new status is different from the previous status. chapter 4 registers 327 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information cmd3 is a command-style register. this register is reset by reset_l. 9 mpplba. write mode n. magic packet physical logical broadcast accept .read-write; if mpplba is at its default value of 0, the controller only detects a magic packet frame if the destination address of the packet matches the content of the physical address register (padr). if mpplba is set to 1, the destination address of the magic packet frame can be unicast, multicast, or broadcast. note that the setting of mpplba only affects the address detection of the magic packet frame. the magic packet frame s data sequence must be made up of 16 consecutive physical addresses (padr[47:0]) regardless of what kind of destination address it has. 8 bkprs_en. write mode n. back pressure enable . read-write; back pressure is enabled when (1) this bit is set, (2) the device is operating in half-duplex mode, and (3) the receiver is in the congested state. 7 valbit0 . value bit for byte 0 . read-write. the value of this bit is written to any bits in the cmd3 register that correspond to bits in the cmd3[6:0] bit map eld that are set to 1. 6:3 reserved. 2 reset_phy_pulse. write mode n. external phy reset pulse . write-only. write-only, always reads 0. writing a 1 to this bit causes the phy_rst pin to assert for a duration speci ed by the reset_phy_width (ctrl1, bits [20:16]) register. reset_phy_pulse and reset_phy should not be set at the same time. 1 reset_phy. write mode n. external phy reset . read-write. the phy_rst pin asserts when reset_phy is set to 1 and deasserts when reset_phy is cleared to 0. reset_phy_pulse and reset_phy should not be set at the same time. 0 phy_rst_pol. write mode n. phy_rst pin polarity . read-write; if 0, phy_rst is active high. if 1, phy_rst is active low. bits description 328 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller command 7 (cmd7) enc064 default: 0000_0000h attribute: read-write. cmd7 is a command-style register. this register is reset when power is ?st applied to the device (power-on reset). the contents of this register are not affected by the state of reset_l. bits description 31 valbit3 . value bit for byte 3 . read-write. the value of this bit is written to any bits in the cmd7 register that correspond to bits in the cmd7[30:24] bit map eld that are set to 1. 30:24 reserved. 23 valbit2 . value bit for byte 2 . read-write. the value of this bit is written to any bits in the cmd7 register that correspond to bits in the cmd7[22:16] bit map eld that are set to 1. 22:16 reserved. 15 valbit1 . value bit for byte 1. read-write. the value of this bit is written to any bits in the cmd7 register that correspond to bits in the cmd7[14:8] bit map eld that are set to 1. 14:8 reserved. 7 valbit0 . value bit for byte 0 . read-write. the value of this bit is written to any bits in the cmd7 register that correspond to bits in the cmd7[6:0] bit map eld that are set to 1. 6:5 reserved. 4 pmat_save_match. write mode 3 . when this bit is 1, the wake-up frame that caused the pme status bit to be set is saved in the receive fifo so that it can be retrieved by the host cpu after it wakes up. when this bit is 0, the wake-up frame is discarded. 3 pmat_mode.pattern match mode . write mode sn. writing a 1 to this bit enables pattern match mode. this bit should be set only after the pattern match ram has been programmed. 2 reserved. 1 mpen_sw. magic packet mode enable . write mode sn. the controller enters the magic packet mode when this bit is set to 1. 0 lcmode_sw. link change wake-up mode . write mode sn. when this bit is set to 1, the lc_det bit in stat0 gets set when the mii auto polling logic detects a link change. chapter 4 registers 329 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller control 1 enc06c default: 0001_0111h attribute: see below. this register contains several miscellaneous control bits. each byte of this register controls a single function. it is not necessary to do a read-modify-write operation to change a function's settings if only a single byte of the register is written. this register is reset by reset_l. bits description 31:22 reserved. 20:16 reset_phy_width. read-write; write mode 2. duration of phy reset pulse initiated by setting phy_reset_pulse in units of 1.3 microseconds. 15:10 reserved. 9:8 xmtsp. transmit start point . read-write; write mode n. xmtsp controls the point at which preamble transmission attempts to commence in relation to the number of bytes written to the mac transmit fifo for the current transmit frame. when the entire frame is in the mac transmit fifo, transmission starts regardless of the value in xmtsp. if rex_uflo is set, no frame data is overwritten until the frame has been transmitted or discarded. otherwise, no data is overwritten until at least 64 bytes have been transmitted. note that when xmtsp = 11b, transmission does not start until the complete frame has been copied into the transmit fifo. this mode is useful in a system where high latencies cannot be avoided. 7:5 reserved. 4 cache_align. pci bus burst align is always set . read-only. . if a burst transfer starts in the middle of a cache line, the transfer stops at the rst cache line boundary. 3:0 burst_limit. pci bus burst limit is xedat1 . read-only. all burst transfers end at the rst cache line boundary. xmtsp[1:0] bytes written 00 16 01 64 10 128 11 full frame 330 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller control 2 enc070 default: 0000_0004h attribute: read-write; write mode 1. this register contains several miscellaneous control bits. each byte of this register controls a single function. it is not necessary to do a read-modify-write operation to change a function's settings if only bits description 31:10 reserved. 9:8 fmdc. fast management data clock . when fmdc is set to 2h the mii management data clock runs at 10 mhz max. the management data clock is then no longer ieee 802.3u-compliant, so setting this bit should be used with care. the accompanying external phy must also be able to accept management frames at the new clock rate. when fmdc is set to 1h, the mii management data clock runs at 5 mhz max. the management data clock is then no longer be ieee 802.3u-compliant, so setting this bit should be used with care. the accompanying external phy must also be able to accept management frames at the new clock rate. when fmdc is cleared to 0h, the mii management data clock runs at 2.5 mhz max and is compliant to ieee 802.3u standards. 7 xphyrst. external phy reset . when xphyrst is set, the controller after an h_reset issues an mii management frame that resets the external phy. this bit is needed when there is no way to ensure the state of the external phy. this bit must be reprogrammed after every h_reset. xphyrst is only valid when the internal network port manager is scanning for a network port. 6 xphyane. external phy auto-negotiation enable . this bit forces the external phy into enabling auto-negotiation. when this bit is cleared to 0, the controller sends an mii management frame disabling auto-negotiation. xphyane is only valid when the internal network port manager is scanning for a network port. 5 xphyfd. external phy full duplex . when set, this bit forces the external phy into full duplex when auto-negotiation is not enabled.xphyfd is only valid when the internal network port manager is scanning for a network port. 4:3 xphysp. external phy speed . when auto-negotiation is disabled, the controller sends a management frame to the external phy to set the data rate based on the contents of this eld. 2:0 apdw. mii auto-poll dwell time . apdw determines the dwell time (or idle time) between mii management frames accesses when auto-poll is turned on. xphysp data rate 00 10 mb/s 01 100 mb/s 1x reserved apdw mdc periods between frames polling period (start frame to start frame) 000 1 27.2 s @ 2.5 mhz 001 128 77.6 s @ 2.5 mhz 010 256 128.8 s @ 2.5 mhz 011 512 231.2 s @ 2.5 mhz 100 1024 436.0 s @ 2.5 mhz 101 2048 845.6 s @ 2.5 mhz 110-111 reserved reserved chapter 4 registers 331 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information a single byte of the register is written. this register is reset by reset_l. lan ethernet controller group a delayed interrupt enc0a8 default: 0000_0000h attribute: read-write; write mode r. this register controls delayed interrupt group a. it allows the user to assign interrupt events to group a and to specify the amount of time or the number of events for which a group a interrupt can be delayed. this register is reset by reset_l. bits description 31:29 reserved. 28 dly_int_a_r0. if 1, rint0 is delayed with event_count_a and max_delay_time_a. 27 dly_int_a_t3. if 1, tint3 is delayed with event_count_a and max_delay_time_a. 26 dly_int_a_t2. if 1, tint2 is delayed with event_count_a and max_delay_time_a. 25 dly_int_a_t1. if 1, tint1 is delayed with event_count_a and max_delay_time_a. 24 dly_int_a_t0. if 1, tint0 is delayed with event_count_a and max_delay_time_a. 23:21 reserved. 20:16 event_count_a. this eld indicates the maximum number of group a interrupt events that can occur before a delayed interrupt signal occurs. 15:11 reserved. 10:0 max_delay_time_a. this eld indicates the maximum time (measured in units of 10 s) that can elapse after a group a interrupt event occurs before a delayed interrupt signal occurs. 332 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller group b delayed interrupt enc0ac default: 0000_0000h attribute: read-write; write mode r. this register controls delayed interrupt group b. it allows the user to assign interrupt events to group b and to specify the amount of time or the number of events for which a group b interrupt can be delayed. this register is reset by reset_l. bits description 31:29 reserved. 28 dly_int_b_r0. if 1, rint0 is delayed with event_count_b and max_delay_time_b. 27 dly_int_b_t3. if 1, tint3 is delayed with event_count_b and max_delay_time_b. 26 dly_int_b_t2. if 1, tint2 is delayed with event_count_b and max_delay_time_b. 25 dly_int_b_t1. if 1, tint1 is delayed with event_count_b and max_delay_time_b. 24 dly_int_b_t0. if 1, tint0 is delayed with event_count_b and max_delay_time_b. 23:21 reserved. 20:16 event_count_b. this eld indicates the maximum number of group b interrupt events that can occur before a delayed interrupt signal occurs. 15:11 reserved. 10:0 max_delay_time_b. this eld indicates the maximum time (measured in units of 10 s) that can elapse after a group b interrupt event occurs before a delayed interrupt signal occurs. chapter 4 registers 333 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller flow control enc0c8 default: 0000_0000h attribute: see below. the upper 16 bits of the flow register is a command-style register while the lower 16 bits are a normal register. this register is reset by reset_l. bits description 31 valbit3. value bit for byte 3 . read-write. the value of this bit is written to any bits in this register that correspond to any bit of this register set to 1 in the range 30:24. 30 pause_len_chg. write mode r. pause length change . read-write; before changing the value of pause_len, the host cpu must wait until pause_len_chg = 0 and then write to this register setting pause_len_chg to 1 and setting pause_len to the new value. 29:24 reserved. 23 valbit2. value bit for byte 2 . read-write. the value of this bit is written to any bits in this register that correspond to any bit of this register set to 1 in the range 22:16. 22 ftpe. write mode n. force transmit pause enable . read-write; when this bit is set, mac control pause frames may be transmitted, regardless of the results of autonegotiation. 21 frpe. write mode n. force receive pause enable . read-write; when this bit is set, mac control pause frames received are recognized and obeyed, regardless of the results of autonegotiation. 20 napa. write mode n. negotiate asymmetric pause ability . read-write; this bit is loaded into the asm_dir advertisement bit of phy register 4 prior to starting autonegotiation. 19 npa. write mode r. negotiate pause ability . read-write; this bit is loaded into the pause advertisement bit of phy register 4 prior to starting autonegotiation. 18 fixp. write mode r. fixed length pause . read-write; when this bit is set to 1, all mac control pause frames transmitted from the device contain a request_operand eld that is copied from the pause_len eld of this register. when this bit is cleared to 0, a pause frame with its request_operand eld set to 0ffffh is sent when fccmd is set to 1. a pause frame with its request_operand eld cleared to 0000h is sent when fccmd becomes 0. 17 reserved. 16 fccmd. write mode r. flow control command . read-write; this bit can be used by the host to send pause frames or to enable or disable half-duplex back-pressure mode. in full-duplex mode, if the fixp bit is 1, fccmd is a write-only bit. when fccmd is set to 1, a pause frame is sent with request_operand copied from the pause_len eld of this register. if the fixp bit is 0, fccmd is a read-write bit. when fccmd is set to 1, a pause frame is sent with its request_operand eld lled with all 1s. when fccmd is cleared to 0, a pause frame is sent with its request_operand eld lled with all 0s. in half-duplex mode, fccmd is a read-write bit. setting fccmd to 1 puts the mac into back-pressure mode. clearing fccmd to 0 disables back-pressure mode. 15:0 pause_len. write mode r. pause length . read-write; the contents of this eld are copied into the request_operand elds of mac control pause frames that are transmitted while the fixp pin in this register has the value 1. the protocol for changing pause_len is: 1) read flow until pause_len_chg is 0. 2) write flow with pause_len_chg = 1 and new value of pause_len. pause_len_chg clears when write is complete, but the driver need not poll for this. 334 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller inter frame spacing enc18d default: 60h attribute: read-write; write mode n. this register is reset by reset_l. lan ethernet controller interframe spacing part 1 enc18c default: 3ch attribute: read-write; write mode n. this register is reset by reset_l. bits description 7:0 ipg. inter packet gap . this value indicates the minimum number of network bit times after the end of a frame that the transmitter waits before it starts transmitting another frame. in half-duplex mode the end of the frame is determined by crs, while in full-duplex mode the end of the frame is determined by tx_en. the ipg value can be adjusted to compensate for delays through the external phy device. ipg should be programmed to the nearest nibble. the two least signi cant bits are ignored. for example, programming ipg to 63h has the same effect as programming it to 60h. caution: use this parameter with care. by lowering the ipg below the ieee 802.3 standard 96 bit times, the network controller can interrupt normal network behavior. ipg must not be set to a value less than 64 (decimal). bits description 7:0 ifs1. interframespacingpart1 . changing ifs1 allows the user to program the value of the interframe- spacepart1 timing. the network controller sets the default value at 60 bit times (3ch). see section 3.10.4.3.1, "medium allocation," on page 86 for more details. the equation for setting ifs1 when ipg 96 bit times is: ifs1 = ipg 36 bit times ipg should be programmed to the nearest nibble. the two least signi cant bits are ignored. for example, programming ipg to 63h has the same effect as programming it to 60h. chapter 4 registers 335 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller interrupt 0 enc038 default: 0000_0000h attribute: see below. bits description 31 intr. interrupt summary . read-only. this bit indicates that one or more of the other interrupt bits in this register are set and the associated enable bit or bits in inten0 are also set. if intren in cmd0 is set to 1 and intr is set, inta is active. intr is read-only. intr is cleared by clearing all of the active individual interrupt bits that have not been masked out. 30 intpn. interrupt pin value .read-only. this bit indicates that the inta_l pin is asserted, that is, both the intr bit (int0[31]) and the intren bit (cmd0[1]) are 1. 29:28 reserved. 27 lcint. link change interrupt . read, write 1b to clear; write mode r. this bit is set when the port manager detects a change in the link status of the external phy. 26 apint5. auto-poll interrupt from register 5 . read, write 1b to clear; write mode r. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 5. 25 apint4. auto-poll interrupt from register 4 . read, write 1b to clear; write mode r. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 4. 24 apint3. auto-poll interrupt from register 3 . read, write 1b to clear; write mode r. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 3. 23 reserved. 22 apint2. auto-poll interrupt from register 2 . read, write 1b to clear; write mode r. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 2. 21 apint1. auto-poll interrupt from register 1 . read, write 1b to clear; write mode r. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 1. 20 apint0. auto-poll interrupt from register 0 . read, write 1b to clear; write mode r. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 0. 19 miipdint. mii phy detect transition interrupt . read, write 1b to clear; write mode r. the mii phy detect transition interrupt is set by the controller whenever the miipd bit in stat0 transitions from 0 to 1 or vice versa. 18 reserved. 17 mccint. mii management command complete interrupt . read, write 1b to clear; write mode r. the mii management command complete interrupt is set by the controller when a read or write operation to the mii data port (phy access register) is complete. 16 mreint. mii management read error interrupt . read, write 1b to clear; write mode r. the mii read error interrupt is set by the controller to indicate that the currently read register from the external phy is invalid. the contents of the phy access register are incorrect and that the operation should be performed again. the indication of an incorrect read comes from the phy. during the read turnaround time of the mii management frame the external phy should drive the mdio pin to a low state. if this does not happen, it indicates that the phy and the controller have lost synchronization. 15 reserved. 14 spndint. suspend interrupt . read, write 1b to clear; write mode r. his bit is set when a receiver or transmitter suspend operation has nished. 336registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information int0 identi?s the source or sources of an interrupt. with the exception of intr and intpn, all bits in this register are ?rite 1 to clear?so that the cpu can clear the interrupt condition by reading the register and then writing back the same data that it read. writing a 0 to a bit in this register has no effect. this register is reset by reset_l. in addition, tintx, rint0, rint_sum, tint_sum, spndint, and mpint are reset when the run bit is cleared. 13 mpint. magic packet interrupt . read, write 1b to clear; write mode r. magic packet interrupt is set by the controller when the device is in the magic packet mode and the controller receives a magic packet frame. 12 reserved. 11 tint3. read, write 1b to clear; write mode r. transmit interrupt is set by the controller after the own bit in the last descriptor of a transmit frame in this particular ring has been cleared to indicate the frame has been copied to the transmit fifo. 10 tint2. read, write 1b to clear; write mode r. transmit interrupt is set by the controller after the own bit in the last descriptor of a transmit frame in this particular ring has been cleared to indicate the frame has been copied to the transmit fifo. 9 tint1. read, write 1b to clear; write mode r. transmit interrupt is set by the controller after the own bit in the last descriptor of a transmit frame in this particular ring has been cleared to indicate the frame has been copied to the transmit fifo. 8 tint0. read, write 1b to clear; write mode r. transmit interrupt is set by the controller after the own bit in the last descriptor of a transmit frame in this particular ring has been cleared to indicate the frame has been copied to the transmit fifo. 7 uint. user interrupt . read, write 1b to clear; write mode r. uint is set by the controller after the host has issued a user interrupt command by setting uintcmd in the cmd0 register. 6:5 reserved. 4 stint. software timer interrupt . read, write 1b to clear; write mode r. the software timer interrupt is set by the controller when the software timer counts down to 0. the software timer immediately loads the contents of the software timer value register, stval, into the software timer and begins counting down. 3:1 reserved. 0 rint0. read, write 1b to clear; write mode r. receive interrupt is set by the controller after the last descriptor of a receive frame for this ring has been updated by writing a 0 to the ownership bit. bits description chapter 4 registers 337 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller interrupt 0 enable enc040 default: 0000_0000h attribute: read-write; write mode r. bits description 31 valbit3. value bit for byte 3 . the value of this bit is written to any bits in the inten0 register that correspond to bits in the inten0[30:24] bit map eld that are set to 1. 30:28 reserved. 27 lcinten. link change interrupt enable . when this bit is set, the intr bit will be set when the lcint bit in int0 is set. 26 apint5en. auto-poll interrupt from register 5 enable . when this bit is set, the intr bit will be set when the apint5 bit in int0 is set. 25 apint4en. auto-poll interrupt from register 4 enable . when this bit is set, the intr bit will be set when the apint4 bit in int0 is set. 24 apint3en. auto-poll interrupt from register 3 enable . when this bit is set, the intr bit will be set when the apint3 bit in int0 is set. 23 valbit2. value bit for byte 2 . the value of this bit is written to any bits in the inten0 register that correspond to bits in the inten0[22:16] bit map eld that are set to 1. 22 apint2en. auto-poll interrupt from register 2 enable . when this bit is set, the intr bit will be set when the apint2 bit in int0 is set. 21 apint1en. auto-poll interrupt from register 1 enable . when this bit is set, the intr bit will be set when the apint1 bit in int0 is set. 20 apint0en. auto-poll interrupt from register 0 enable . when this bit is set, the intr bit will be set when the apint0 bit in int0 is set. 19 miipdinten. mii phy detect transition interrupt enable . when this bit is set, the intr bit will be set when the miipdtint bit in int0 is set. 18 reserved. 17 mccinten. mii management command complete interrupt enable . when this bit is set, the intr bit will be set when the mccint bit in int0 is set. 16 mreinten. mii management read error interrupt enable . when this bit is set, the intr bit will be set when the mreint bit in int0 is set. 15 valbit1. value bit for byte 1 . the value of this bit is written to any bits in the inten0 register that correspond to bits in the inten0[14:8] bit map eld that are set to 1. 14 spndinten. suspend interrupt enable . when this bit is set, the intr bit will be set when the spndint bit in int0 is set. 13 mpinten. magic packet interrupt enable . when this bit is set, the intr bit will be set when the mpint bit in int0 is set. 12 reserved. 11 tinten3. transmit interrupt enable . when this bit is set, the intr bit will be set when the tint bit for this particular ring in int0 is set. 10 tinten2. transmit interrupt enable . when this bit is set, the intr bit will be set when the tint bit for this particular ring in int0 is set. 9 tinten1. transmit interrupt enable . when this bit is set, the intr bit will be set when the tint bit for this particular ring in int0 is set. 8 tinten0. transmit interrupt enable . when this bit is set, the intr bit will be set when the tint bit for this particular ring in int0 is set. 7 valbit0. value bit for byte 0 . the value of this bit is written to any bits in the inten0 register that correspond to bits in the inten0[6:0] bit map eld that are set to 1. 338 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information this register allows the software to specify which types of interrupt events cause the intr bit in the interrupt0 register to be set, which in turn causes the pirqa_l pin to be asserted if the intren bit in cmd0 is set. each bit in this register corresponds to a bit in the interrupt0 register. setting a bit in this register enables the corresponding bit in the interrupt0 register to cause the intr bit to be set. inten0 is a command style register. the high order bit of each byte of this register is a ?alue?bit that speci?s the value to be written to selected bits of the register. the seven low order bits of each byte make up a bit map that selects which register bits will be altered. this register is reset by reset_l. lan ethernet controller logical address filter enc168 default: 0000_0000_0000_0000h attribute: read-write; write mode r. this register is reset by reset_l. 6:5 reserved. 4 stinten. software timer interrupt enable . when this bit is set, the intr bit will be set when the stint bit in int0 is set. 3:1 reserved. 0 rinten0. receive interrupt enable . when this bit is set, the intr bit will be set when the rint0 bit in int0 is set. bits description 63:0 ladrf. logical address filter, ladrf[63:0] . this register contains a 64-bit mask that is used to accept incoming logical (or multicast) addresses. if the rst bit in the incoming address (as transmitted on the wire) is a 1, the destination address is a logical address. a logical address is passed through the crc generator to produce a 32-bit result. the high order 6 bits of this result are used to select one of the 64-bit positions in the logical address filter. if the selected lter bit is set, the address is accepted, and the frame is copied into host system memory. the logical address filter is used in multicast addressing schemes. the acceptance of the incoming frame based on the lter value indicates that the message may be intended for the node. it is the responsibility of the host cpu to compare the destination address of the stored message with a list of acceptable multicast addresses to determine whether or not the message is actually intended for the node. bits description chapter 4 registers 339 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller mib address enc14 default: 0000h attribute: see below. used for indirect access to the mib_data register. this register is reset by reset_l. lan ethernet controller mib data access enc10 default: ????_????h attribute: read-only. access to this data register is indirect by way of the mib_addr register. protocol is similar to phy access protocol except no interrupt is available as accesses end within a short time. the access protocol for a read access is: 1. read mib_addr until mib_cmd_active is 0. 2. write mib_addr with mib_rd_cmd = 1 and mib_addr set to the desired address. 3. read mib_addr until mib_cmd_active is 0. the value is in the mib_data register. data transfers are 32 bits wide for mib. bits description 15 mib_cmd_active. command active . read-only. a value of 1 indicates that an access cycle is in progress. the host cpu must not write to this register while this bit is 1. a value of 0 indicates that the previous access cycle has completed and a new access cycle may be started. 14 reserved. 13 mib_rd_cmd. read command . read, write 1b to clear; write mode r. setting this bit to 1 starts a read access cycle. 12 mib_clear. read, write 1b to clear; write mode r. setting this bit to 1 causes all mib locations to be set to all zeros. 11:6 reserved. 5:0 mib_address. read-write; write mode r. the address of the desired table entry. bits description 31:0 mib_data. mib register contents . may be cleared using mib_clear bit in mib_addr register. 340 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller physical address enc160 default: 0000_0000_0000h attribute: read-write; write mode r. this register is reset by reset_l. lan ethernet controller phy access enc0d0 default: 0000_0000h attribute: see below. this register gives the host cpu indirect access to the mii management bus (mdc/mdio). through this register the host cpu can read or write any external phy register that is accessible through the bits description 47:0 mac physical address, padr[47:0]. this register contains 48-bit, globally unique station address assigned to this device. if the least signi cant bit of the rst byte of a received frame is 0, the destination address of the frame is a unicast address, which is compared with the contents of the padr. if this bit is 0 and the frame s destination address exactly matches the contents of padr, the frame is accepted and copied into the host system memory. the byte order is such that padr[7:0] corresponds to the rst address byte transferred over the network. unicast address matching can be disabled by setting the disable receive physical address bit (dcrvpa, bit 18 in cmd2). if drcvpa is set to 1, a match of a frame s destination address with the contents of padr does not cause the frame to be accepted and copied into the host memory. bits description 31 phy_cmd_active. phy command active . read-only. this bit is automatically set to 1 while the phy access logic is busy. the content of the phy_data eld is invalid while this bit is 1. 30 phy_wr_cmd. phy write command . write-only. setting this bit to 1 starts the process of writing the data in the phy_data eld to the external phy register speci ed by the phy_addr and phy_reg_addr elds. 29 phy_rd_cmd. phy read command . write-only. setting this bit to 1 starts the process of reading the external phy register speci ed by the phy_addr and phy_reg_addr elds. 28 phy_rd_err. phy read error . read-only. this bit is automatically set if the previous command was phy_rd_cmd and a read error was detected. 27 reserved. 26 phy_pre_sup. preamble suppression . read-write. if this bit is set, the mii management frame is sent without a preamble. before setting this bit the host cpu must make sure that the external phy addressed by the phy_addr eld is capable of accepting mii management frames without preambles. 25:21 phy_addr. phy address . read-write. the address of the external phy device to be accessed. 20:16 phy_reg_addr. phy register address . read-write. the address of the register in the external phy device to be accessed. 15:0 phy_data. phy data . read-write.data written to or read from the external phy register speci ed by phy_addr and phy_reg_addr. chapter 4 registers 341 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information mii management bus. when the host cpu sets the phy write command or phy read command bit, the appropriate management frame is sent over the management bus. the phy access protocol is: 1. read phy_access until phy_cmd_active is 0. 2. write phy_wr_cmd or phy_rd_cmd, phy_pre_sup, phy_addr, phy_reg_addr and, if write, phy_data to phy_access register. 3. if read, wait for mccint interrupt or read phy_access register until phy_cmd_active is 0. this register is reset by reset_l. lan ethernet controller onnow pattern 0 enc190 default: 0000_000?h attribute: see below. this register is used to control and indirectly access the pattern match ram (pmr). access protocol is: 1. ensure pmat_mode is 0 either by program logic or by reading cmd7 or pmat0. the pmr_active bit is a read-only copy of pmat_mode. 2. for write, write data to pmat1 and then to pmat0 with pmr_wr_cmd set to 1 and pmr_addr set to the desired memory address. specify the bank with pmr_bank. 3. for read, write pmat0 with pmr_rd_cmd set to 1 and pmr_addr set to the desired memory address. 4. for read, read data from pmat0 and pmat1. bits [31:16] of this register are reset by reset_l. bits [15:0] are never reset. bits description 31 pmr_active. read-only. read-only copy of pmat_mode. 30 pmr_wr_cmd. pmr write command . write-only; write mode 3. setting this bit to 1 causes the data in the pmat1 register and the pmr_b4 eld of this register to be written to the word in the pattern match ram speci ed by the pmr_addr eld of this register. 29 pmr_rd_cmd. pmr read command . write-only; write mode 3. setting this bit to 1 causes the word in the pattern match ram speci ed by the pmr_addr eld of this register to be read into the pmat1 register and the pmr_b4 eld of this register. 28:23 reserved. 22:16 pmr_addr. pattern match ram address . read-write; write mode 3. these bits are the pattern match ram address to be written to or read from 15:8 reserved. 7:0 pmr_b4. pattern match ram byte 4 . read-write; write mode 3. this byte is written into or read from byte 4 of the selected word of the pattern match ram. 342 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller onnow pattern 1 enc194 default: ????_????h attribute: read-write; write mode 3. this register is used to indirectly access the pattern match ram (pmr). this register is never reset. lan ethernet controller receive ring length enc150 default: 0000h attribute: read-write; write mode n. this register is reset by reset_l. lan ethernet controller sram boundary enc17a default: 0008h attribute: read-write; write mode n. this register is reset by reset_l. bits description 31:24 pmr_b3. pattern match ram byte 3 . this byte is written into or read from byte 3 of the selected word of the pattern match ram. 23:16 pmr_b2. pattern match ram byte 2 . this byte is written into or read from byte 2 of the selected word of the pattern match ram. 15:8 pmr_b1. pattern match ram byte 1 . this byte is written into or read from byte 1 of the selected word of the pattern match ram. 7:0 pmr_b0. pattern match ram byte 0 . this byte is written into or read from byte 0 of the selected word of the pattern match ram. bits description 15:0 rcv_ring_len. this value indicates the number of descriptors in the receive descriptor ring. bits description 15:5 reserved. 4:0 sram_bnd. speci es the size of the transmit buffer portion of the sram in units of 512-byte pages. for example, if sram_bnd is set to 10, then 5120 bytes of the sram is allocated for the transmit buffer and the rest is allocated for the receive buffer. the transmit buffer in the sram begins at address 0 and ends at the address (sram_bnd*512)-1. therefore, the receive buffer always begins on a 512-byte boundary. the minimum allowed number of pages for normal network operation is four, and the maximum is sram_size 4. values larger than this cause incorrect behavior. chapter 4 registers 343 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller sram size enc178 default: 0010h attribute: read-write; write mode n. this register is reset by reset_l. bits description 15:5 reserved. 4:0 sram_size. speci es the size of the internal sram in units of 512-byte pages. sram_size should normally be set to 16, since the size of the sram is 8192 bytes. sram_size can be set to a lower number for debugging purposes. 344 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller status 0 enc030 default: 0001_0000h attribute: see below. bits [12:10] of this register are reset by power-on reset. bits [9:0] of this register are reset by reset_l. bits description 31:13 reserved. 12 pmat_det. pattern match detected . read, write 1b to clear; write mode n. this bit indicates that an onnow pattern match has occurred while the device was in the onnow pattern match mode. this bit can be cleared to 0 by writing 1 to stat0, bit 12. 11 mp_det. magic packet frame detected . read, write 1b to clear; write mode n. this bit indicates that a magic packet pattern match has occurred while the device was in the magic packet mode. this bit can be cleared to 0 by writing 1 to stat0, bit 11. 10 lc_det. link change detected . read, write 1b to clear; write mode n. this bit indicates that a change in the link status of the external phy device has been detected while the device was in the link change wake-up mode. this bit can be cleared to 0 by writing 1 to stat0, bit 10. 9:7 speed. speed . read-only. this eld indicates the bit rate at which the network is running. the following encoding is used: 000=unknown, 001=reserved, 010=10 mb/s, 011=100 mb/s, 100-111 are reserved. 6 full_duplex. full duplex . read-only. this bit is set when the device is operating in full-duplex mode. 5 link_status. link status . read-only. this bit is set to the value of the link status bit in the status register (r1) of the default external phy. (the default external phy is the phy addressed by the ap_phy0_addr eld of the autopoll0 register.) this bit is updated each time the external phy s status register is read, either by the auto-poll state machine, by the network port manager, or by a cpu-initiated read. however, when the force link status bit in cmd3 is set to 1, this bit is forced to 1, regardless of the contents of the external phy s status register. 4 autoneg_complete. auto-negotiation complete . read-only. this bit is set to the value of the auto-negotiation complete bit in register 1 of the external phy as determined by the most recent port manager polling cycle. 3 miipd. mii phy detect . read-only. miipd re ects the quiescent state of the mdio pin. miipd is continuously updated whenever there is no management operation in progress on the mii interface. when a management operation begins on the interface, the state of miipd is preserved until the operation ends, when the quiescent state is again monitored and continuously updates the miipd bit. when the mdio pin is at a quiescent low state, miipd is cleared to 0. when the mdio pin is at a quiescent high state, miipd is set to 1. any transition on the miipd bit sets the miipdtint bit in int0. 2 rx_suspended. receiver suspended . read-only. this bit has the value 1 while the receiver is suspended, and it has the value 0 when the receiver is not suspended. 1 tx_suspended. transmitter suspended . read-only. this bit has the value 1 while the transmitter is suspended, and it has the value 0 when the transmitter is not suspended. 0 running. read-only. this bit is a read-only alias of the run bit in cmd0. when this bit is set, the device is enabled to transmit and receive frames and process descriptors. note that even though running is set, the receiver or transmitter might be disabled because rx_spnd or tx_spnd is set (in cmd0). chapter 4 registers 345 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information lan ethernet controller spare enc000 default: 0000_0000h attribute: read-only. lan ethernet controller software timer value enc0d8 default: ffffh attribute: read-write; write mode r. this register is reset by reset_l. lan ethernet controller transmit ring 0 length enc140 default: 0000h attribute: read-write; write mode. this register is reset by reset_l. lan ethernet controller transmit ring 1 length enc144 default: 0000h attribute: read-write; write mode. this register is reset by reset_l. bits description 31:3 reserved. 1:0 spare. these bits are hardwired to 0h. bits description 15:0 stval. software timer value . stval controls the maximum time for the software timer to count before generating the stint (intr, bit 4) interrupt. the software timer is a free-running timer that is started upon the rst write to stval. after the rst write, the software timer continually counts and sets the stint interrupt at the stval period. the stval value is interpreted as an unsigned number with a resolution of 10.24 s. for instance, if stval is set to 48,828 (0bebch), the software timer period is 0.5 s. the default value (0ffffh) corresponds to 0.6710784 s. setting stval to a value of 0 results in erratic behavior. bits description 15:0 xmt_ring0_len. this value indicates the number of descriptors in transmit descriptor ring 0. bits description 15:0 xmt_ring1_len. this value indicates the number of descriptors in transmit descriptor ring 1. 346registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information lan ethernet controller transmit ring 2 length enc148 default: 0000h attribute: read-write; write mode. this register is reset by reset_l. lan ethernet controller transmit ring 3 length enc14c default: 0000h attribute: read-write; write mode. this register is reset by reset_l. lan ethernet controller transmit ring limit enc07c default: 0000_0000h attribute: see below. event counters limit the number of consecutive high priority transmissions to prevent the lower priority transmit rings from being locked out by higher priority rings. see transmitter fairness algorithm section. this register is reset by reset_l. 4.10.4 receive descriptors figure 32 shows the format of receive descriptors. figure 33 shows the format of the flags ?ld of a receive descriptor. bits description 15:0 xmt_ring2_len. this value indicates the number of descriptors in transmit descriptor ring 2. bits description 15:0 xmt_ring3_len. this value indicates the number of descriptors in transmit descriptor ring 3. bits description 31:24 xmt_ring3_limit. transmit ring3 limit . read-only. always 0. ring3 is highest priority and cannot be locked out. 23:16 xmt_ring2_limit. transmit ring2 limit .read-write; write mode n. no limit if 0. 15:7 xmt_ring1_limit. transmit ring1 limit . read-write; write mode n. no limit if 0. 7:0 xmt_ring0_limit. transmit ring0 limit . read-write; write mode n. no limit if 0. chapter 4 registers 347 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information figure 32. receive descriptor format the name flags in this ?ure stand for a collection of bits that are displayed in figure 33 below. figure 33. format of flags in receive descriptor, offset 08h table 66 on page 347 shows the receive descriptor bit de?itions. offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 109876543210 00h user space 04h tci[15:0] mcnt{15:0] 08h flags res bcnt[15:0] 0ch rbadr[31:0] offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 109876543210 08h bcnt[15:0] table 66. receive descriptor bit de nitions offset bit name description 0 31:0 reserved 4 31:16 tci[15:0] vlan tag control information copied from the received frame. 15:0 mcnt message byte count is the number of bytes of the received message written to the receive buffer. this is the actual frame length (including fcs) unless stripping is enabled and the length eld is < 46 bytes. in this case, mcnt is 14 + length_ eld. mcnt can take values in the range 15 to 59 and values greater than or equal to 64. mcnt is expressed as an unsigned binary integer. mcnt is valid only when err is clear and enp is set. mcnt is written by the network controller and cleared by the host. own err fra m ofl o crc buff 348 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 831 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the network controller (own = 1). the host sets the own bit after it has emptied the buffer pointed to by the descriptor entry. the network controller clears the own bit after lling the buffer that the descriptor points to. both the network controller and the host must not alter a descriptor entry after it has relinquished ownership. 830 err error summary . err is the or of fram, oflo, crc, and buff. err is set by the network controller and cleared by the host. 829 fram framing error indicates that the incoming frame contains a non-integer multiple of eight bits and there was an fcs error. if there was no fcs error on the incoming frame, then fram is not set even if there was a non-integer multiple of eight bits in the frame. fram is not valid in internal loopback mode. fram is valid only when enp is set and oflo is not. fram is set by the network controller and cleared by the host. 828 oflo over ow error indicates that the receiver has lost all or part of the incoming frame, due to an inability to move data from the receive fifo into a memory buffer before the internal fifo over owed. oflo is set by the network controller and cleared by the host. 827 crc crc indicates that the receiver has detected a crc (fcs) error on the incoming frame. crc is valid only when enp is set and oflo is not. crc is set by the network controller and cleared by the host. crc is also set when the controller receives an rx_er indication from the external phy through the mii. 826 buff buffer error . if this bit is set, the end of this frame was lost because the next descriptor was not available when it was needed. the rcvmisspkts mib counter is also incremented when this error occurs. 825 stp start of packet indicates that this is the rst buffer used by the network controller for this frame. if stp and enp are both set to 1, the frame ts into a single buffer. otherwise, the frame is spread over more than one buffer. stp is set by the controller and cleared by the host. 824 enp end of packet indicates that this is the last buffer used by the network controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame ts into one buffer and there is no data chaining. enp is set by the controller and cleared by the host. 8 23 reserved 822 pam physical address match is set by the network controller when it accepts the received frame due to a match of the frame's destination address with the content of the physical address register. pam is valid only when enp is set. pam is set by the network controller and cleared by the host. table 66. receive descriptor bit de nitions (continued) offset bit name description chapter 4 registers 349 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 4.10.5 transmit descriptors figure 34 shows the format of transmit descriptors. figure 35 shows the format of the tflags1 ?ld of a transmit descriptor. figure 34. transmit descriptor format the name tflags1 in this ?ure stands for a collection of bits that are displayed in figure 35 below. 821 lafm logical address filter match is set by the network controller when it accepts the received frame based on the value in the logical address lter register. lafm is valid only when enp is set. lafm is set by the controller and cleared by the host. note that if drcvbc (cmd2, bit 17) is cleared to 0, only bam, but not lafm is set when a broadcast frame is received, even if the logical address filter is programmed in such a way that a broadcast frame would pass the hash lter. if drcvbc is set to 1 and the logical address filter is programmed in such a way that a broadcast frame would pass the hash lter, lafm is set on the reception of a broadcast frame. 820 bam broadcast address match is set by the network controller when it accepts the received frame, because the frame's destination address is of the type 'broadcast.' bam is valid only when enp is set. bam is set by the controller and cleared by the host. 8 19:18 tt[1:0] vlan tag type . indicates what type of vlan tag, if any, is included in the received frame. 00 = reserved 01 = frame is untagged 10 = frame is priority-tagged 11 = frame is vlan-tagged 8 17:16 reserved. 8 15:0 bcnt buffer byte count is the length of the buffer pointed to by this descriptor, expressed as an unsigned integer. this eld is written by the host and unchanged by the network controller. 0ch 31:0 rbadr[31:0] receive buffer address . this eld contains the low order bits of the address of the receive buffer that is associated with this descriptor. offset 31 30 29 28 27:26 25 24 23 22 21 20 19:18 17 16 15-0 00h tflags1 res bcnt[15:0] 04h res tcc[1:0] tci[15:0] 08h tbadr[31:0] 0ch user space table 66. receive descriptor bit de nitions (continued) offset bit name description 350 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information figure 35. format of tflags1 in transmit descriptor, offset 00h table 67 on page 350 shows the transmit descriptor bit de?itions. offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15-0 00h res bcnt[15:0] own add_fcs ltint pri_lock stp enp kill table 67. transmit descriptor bit de nitions offset bit name description 031 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the network controller (own = 1). the host sets the own bit after lling the buffer pointed to by the descriptor entry. the controller clears the own bit after transmitting the contents of the buffer. both the controller and the host must not alter a descriptor entry after it has relinquished ownership. 0 30 reserved location. 029 add_fcs add_fcs dynamically controls the generation of fcs on a frame by frame basis. this bit should be set with the enp bit. however, for backward compatibility, it is recommended that this bit be set for every descriptor of the intended frame. when add_fcs is set, the state of dxmtfcs is ignored and transmitter fcs generation is activated. when add_fcs is cleared to 0, fcs generation is controlled by dxmtfcs. when apad_xmt (cmd2, bit 6) is set to 1, the setting of add_fcs has no effect. add_fcs is set by the host, and is not changed by the network controller. 028 ltint last transmit interrupt . when enabled by the ltinten bit (cmd2, bit 9), ltint is used to suppress interrupts after selected frames have been copied to the transmit fifo. when ltint is cleared to 0 and enp is set to 1, the network controller does not set tintx (int0, bits 8-11) after the corresponding frame has been copied to the transmit fifo. tintx is only set when the last descriptor of a frame has both ltint and enp set to 1. when ltinten is cleared to 0, the ltint bit is ignored. 0 27 reserved. 026 pri_lock priority lock . if pri_lock is set on the rst descriptor of a frame (when stp is set), the transmit ring arbitrator is forced to take the next frame from the same ring as this one. if the rst descriptor of that frame also has pri_lock set, the process continues. when pri_lock is not set in the rst descriptor of a frame, the next frame comes from the ring chosen by the arbiter. pri_lock is ignored if stp is not set. chapter 4 registers 351 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 025 stp start of packet indicates that this is the rst buffer to be used by the network controller for this frame. it is used for data chaining buffers. the stp bit must be set in the rst buffer of the frame, or the controller skips over the descriptor and polls the next descriptor(s) until the own and stp bits are set. stp is set by the host and is not changed by the controller. 024 enp end of packet indicates that this is the last buffer to be used by the controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame ts into one buffer and there is no data chaining. enp is set by the host and is not changed by the controller. 0 23 reserved 022 kill this bit causes the transmission of the corresponding frame to be aborted. if the transmitter has not started sending the frame at the time that the descriptor processing logic encounters the kill bit, no portion of the frame is sent. if part of the frame has been sent, the frame is truncated, and an fcs eld containing the inverse of the correct crc is appended. 0 21:16 reserved. 0 15:0 bcnt buffer byte count is the usable length of the buffer pointed to by this descriptor, expressed as an unsigned integer. this is the number of bytes from this buffer that are to be transmitted by the network controller. this eld is written by the host and is not changed by the network controller. there are no minimum buffer size restrictions. 4 31:18 reserved. 4 17:16 tcc[1:0] vlan tag control command . this eld contains a command that causes the transmitter to add, modify, or delete a vlan tag or to transmit the frame unaltered. 00 = transmit the data in the buffer unaltered 01 = delete the vlan tag (the 13th through 16th bytes of the frame) 10 = insert a vlan tag containing the tci eld from the descriptor 11 = replace the tci eld of the frame with tci data from the descriptor 4 15:0 tci[15:0] tag control information . if the contents of the tcc eld are 10 or 11, the controller transmits the contents of the tci eld as bytes 15 and 16 of the outgoing frame. 8 31:0 tbadr[31:0] transmit buffer address . this eld contains the low order bits of the address of the transmit buffer that is associated with this descriptor. 0ch 31:0 user space user space . reserved for user de ned data. table 67. transmit descriptor bit de nitions (continued) offset bit name description 352 registers chapter 4 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information chapter 5 electrical data 353 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information chapter 5 electrical data 5.1 absolute ratings the ic is not designed to operate beyond the parameters shown in table 68. note: the absolute ratings in the following table and associated conditions must be adhered to in order to avoid damage to the ic and motherboard. systems using the ic must be designed to ensure that the power supply and system logic board do not violate these parameters. violation of the absolute ratings will void the product warranty. table 68. absolute ratings parameter minimum maximum comments vdd_io, vdd_iox, vdd_rtc, vdd_usb 0.5 v 3.6 v vdd_core, vdd_corex, vdd_usba 0.5 v 2.0 v vdd_ldt -0.5 v 1.7 v vdd_ref 0.5 v 5.25 v t case 65 c85 c (under bias) t storage 65 c 150 c notes: 1. this table contains preliminary information, which is subject to change. 354 electrical data chapter 5 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 5.2 operating ranges the ic is designed to provide functional operation if the voltage and temperature parameters are within the limits de?ed in table 69. 5.3 current consumption table 70 provides current consumption of the ic while it is operational. table 69. operating ranges parameter minimum typical maximum vdd_io, vdd_iox, vdd_usb 3.135 v 3.3 v 3.465 v vdd_core, vdd_corex, vdd_usba 1.71 v 1.8 v 1.89 v vdd_ldt 1.14 v 1.2 v 1.26 v vdd_rtc 2.5 v 3.3 v 3.465 v vdd_ref 4.75 v 5.0 v 5.25 v t case 0 c70 c notes: 1. this table contains preliminary information, which is subject to change. table 70. current consumption supply max current s0 s1 s3/s4/s5 g3 vdd_io 60 ma 20 ma n/a n/a vdd_iox 5 ma 5 ma 5 ma n/a vdd_core 300 ma 300 ma n/a n/a vdd_corex 100 ma 100 ma 25 ma n/a vdd_usb 150 ma 2 100 ma 1 ma n/a vdd_usba 250 ma 2 150 ma 0.5 ma n/a vdd_ldt 100 ma 100 ma n/a n/a vdd_rtc n/a n/a n/a 8 a vdd_ref 1 ma 1 ma 1 ma n/a notes: 1. this table contains preliminary information, which is subject to change. 2. this number assumes 6 usb ports transmitting and receiving high-speed traf?. chapter 5 electrical data 355 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information 5.4 signal groups table 71 de?es groups of i/o signals with respect to their electrical behavior. table 71. signal groups signal group signals a host hypertransport technology interface ldtreq_l secondary pci interface ad[31:0], cbe_l[3:0], devsel_l, frame_l, gnt_l[6:0], irdy_l, par, pclk, perr_l, pgnt_l, pirq[a, b, c, d]_l, preq_l, req_l[6:0], serr_l, stop_l, trdy_l lpc bus and legacy support signals lad[3:0], ldrq_l[1:0], lframe_l, spkr enhanced ide interface daddr[p, s][2:0], dcs1[p, s]_l, dcs3[p, s]_l, ddack[p, s]_l, ddrq[p, s], diow[p, s]_l, drst[p, s]_l system management signals acav, agpstop_l, batlow_l, c32khz, clkrun_l, cpusleep_l, cpustop_l, dcstop_l, extsmi_l, fancon[1:0], fanrpm, gpio[31:26, 17, 16, 14, 8, 4], intirq8_l, irq1, irq6, irq12, irq14, irq15, ka20g, kbrc_l, lid, pcistop_l, pme_l, pnpirq[2:0], prdy, pwrbtn_l, pwrok, pwron_l, reset_l, ri_l, rpwron, serirq, slpbtn_l, smbalert[1:0]_l, smbusc1, smbusd1, suspend_l, therm_l universal serial bus interface usboc_l[1:0] ac 97 interface acclk, acrst_l, acsdi[1:0], acsdo, acsync mii interface mii_tx_clk, mii_txd[3:0], mii_tx_en, mii_col, mii_crs, mii_rx_clk, mii_rxd[3:0], mii_rx_dv, mii_rx_err, mii_phy_rst, mii_mdc, mii_mdio test test_l miscellaneous straph[3:0], strapl[3:0] b host hypertransport technology interface lrxcad_h/l[7:0], lrxclk_h/l, lrxctl_h/l, ltxcad_h/l[7:0], ltxclk_h/l, ltxctl_h/l c enhanced ide interface ddata[p, s][15:0], dior[p, s]_l, drdy[p, s] 356electrical data chapter 5 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 5.5 dc characteristics see the hypertransport technology electrical speci?ation for the dc characteristics of the hypertransport interface signals of signal group b. see the usb speci?ation for the dc characteristics of the usb interface signals of signal group d. d universal serial bus interface usb0_h/l[2:0], usb1_h/l[2:0] e host hypertransport technology interface ldtstop_l, ldtrst_l system management signals smbusc0, smbusd0, thermtrip_l f system management signals intruder_l g system management signals rtcx_in, rtcx_out h lpc bus and legacy support signals osc universal serial bus interface usbclk table 72. dc characteristics for signal group a symbol parameter description min max units v il input low voltage 0.3 0.3 vdd_io v v ih input high voltage 0.6 vdd_io vdd_ref + 0.5 v v ol output low voltage; i out = 2 ma 2 , 3 0.1 vdd_io v v oh output high voltage; i out = 2 ma 2 , 3 0.9 vdd_io v i li input leakage current +/ 10 a c in input capacitance 8 pf notes: 1. this table contains preliminary information, which is subject to change. 2. all secondary pci, lpc bus, and ac ?7 interface signals support an output current of i out = +/?6 ma. 3. the smbus 2.0 interface signals smbusc1, smbusd1 support an output current of i out = +/?4 ma. table 71. signal groups (continued) signal group signals chapter 5 electrical data 357 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information table 73. dc characteristics for signal group c symbol parameter description min max units v il input low voltage 0.3 0.3 vdd_io v v ih input high voltage 0.6 vdd_io vdd_ref + 0.5 v v ol output low voltage; i out = 400 a 0.1 vdd_io v v oh output high voltage; i out = 4 ma 0.9 vdd_io v i li input leakage current +/ 10 a c in input capacitance 8 pf notes: 1. this table contains preliminary information, which is subject to change. table 74. dc characteristics for signal group e symbol parameter description min max units v il input low voltage 0.3 0.3 vdd_io v v ih input high voltage 0.6 vdd_io vdd_io + 0.3 v v ol output low voltage; i out = 2 ma 0.1 vdd_io v v oh output high voltage; i out = 2 ma 0.9 vdd_io v i li input leakage current +/ 10 a c in input capacitance 8 pf notes: 1. this table contains preliminary information, which is subject to change. table 75. dc characteristics for signal group f symbol parameter description min max units v il input low voltage 0.1 0.25 v v ih input high voltage 1.0 vdd_io + 0.3 v i li input leakage current 2 +/ 1 a c in input capacitance 8 pf notes: 1. this table contains preliminary information, which is subject to change. 2. for v i = vss or v i > 2 v. table 76. dc characteristics for signal group g symbol parameter description min max units i li input leakage current 10.0 1.0 a 358 electrical data chapter 5 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 5.6 ac characteristics see the hypertransport technology electrical speci?ation for the ac characteristics of the hypertransport interface signals of signal groups a and b. ac characteristics for the pci interface signals, lpc bus, legacy support signals, and system management signals of signal group a match those of the pci speci?ation. see table 78 on page 359 for the ac characteristics of pclk. see table 79 on page 359 for the ac characteristics of osc. see the ata speci?ation for the ac characteristics of the enhanced ide signals of signal groups a and c. see the usb speci?ation for the ac characteristics of the usb interface signals of signal groups d and h. see table 80 on page 360 for the ac characteristics of usbclk. see the ac ?7 speci?ation for the ac characteristics of the ac ?7 interface signals of signal group a. see the ieee 802.3 speci?ation for the ac characteristics of the mii interface signals of signal group a. see the smbus speci?ation for the ac characteristics of the smbus interface signals of signal groups a and f. c in input capacitance 4 pf notes: 1. this table contains preliminary information, which is subject to change. 2. this table applies to rtcx_in only. table 77. dc characteristics for signal group h symbol parameter description min max units v il input low voltage 0.3 0.3 vdd_io v v ih input high voltage 0.6 vdd_io vdd_io + 0.3 v i li input leakage current +/ 10 a c in input capacitance 8 pf notes: 1. this table contains preliminary information, which is subject to change. table 76. dc characteristics for signal group g symbol parameter description min max units chapter 5 electrical data 359 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information table 78. ac characteristics for pclk symbol parameter description min typ max units f frequency 33.333 mhz t s slew rate 2 1 4 v/ns t d duty cycle 3 45 55 % t jc jitter, cycle-to-cycle 4 0 250 ps t ja jitter, accumulated 1000 1000 ps notes: 1. this table contains preliminary information, which is subject to change. 2. measured between 20% and 60% 3. measured on rising and falling edge at 1.5 v 4. measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. table 79. ac characteristics for the osc symbol parameter description min typ max units f frequency 14.318 mhz t s slew rate 2 0.5 2 v/ns t d duty cycle 3 45 55 % t jc jitter, cycle-to-cycle 4 0 500 1000 ps t ja jitter, accumulated 1000 1000 ps notes: 1. this table contains preliminary information, which is subject to change. 2. measured between 20% and 80% 3. measured on rising and falling edge at 1.5 v. 4. measured on rising edge at 1.5 v. maximum difference of cycle time between two adjacent cycles. 360 electrical data chapter 5 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information table 80. ac characteristics for usbclk symbol parameter description min typ max units f frequency 48.008 mhz t s slew rate 2 0.5 2 v/ns t d duty cycle 3 45 55 % t jc jitter, cycle-to-cycle 4 0 200 ps t ja jitter, accumulated -1000 1000 ps notes: 1. this table contains preliminary information, which is subject to change. 2. measured between 20% and 80%. 3. measured on rising and falling edge at 1.5 v. 4. measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. chapter 6pin designations 361 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information chapter 6 pin designations figure 36. bga designations (top side view) 1234567891011121314151617181920212223242526 a nc10 nc12 nc19 nc30 nc21 nc28 dad drs1 drd ys ddat as0 ddat as12 ddat as4 ddat as8 dad drp2 irq14 ddr qp ddat ap13 ddat ap3 ddat ap9 ldrq _l[0] lad2 lad3 irq6 vdd_ rtc lfra me_l ka20 g vdd_ ref a b vss vss vss stra ph3 stra ph0 vss dad drs0 vss ddat as15 ddat as2 vss ddat as6 dcs1 p_l vss diow p_l ddat ap1 vss ddat ap5 drst p_l vss spkr lad0 vss irq1 vss gpio 26 b c vdd_ ldt vdd_ ldt vdd_ ldt vss nc29 nc22 dad drs2 irq15 ddr qs ddat as13 ddat as3 ddat as9 dcs3 p_l dad drp0 dior p_l ddat ap14 ddat ap2 ddat ap10 ddat ap7 osc intir q8_l kbrc _l seri rq gpio 8 vss vss c d lrxc ad_h [1] lrxc ad_l [0] lrxc ad_h [0] vdd_ ldt stra ph1 vdd_ io dcs3 s_l vdd_ io dior s_l ddat as14 vdd_ io ddat as10 ddat as7 vdd_ io ddac kp_l ddat ap15 vdd_ io ddat ap11 ddat ap6 vdd_ io ldrq _l[1] lad1 vdd_ io vss usb1 _l[0] usb1 _h[0] d e lrxc ad_l [1] vss nc2 stra ph2 nc20 nc9 dcs1 s_l ddac ks_l diow s_l ddat as1 ddat as11 ddat as5 drst s_l dad drp1 drd yp ddat ap0 ddat ap12 ddat ap4 ddat ap8 gpio 29 prdy irq12 vss usb1 _l[1] usb1 _h[1] vss e f lrxc ad_h [3] lrxc ad_l [2] lrxc ad_h [2] vss nc7 vss vdd_ core vdd_ core vdd_ core vdd_ core vdd_ io vdd_ io vdd_ io vdd_ io vss test _l gpio 31 vss usb1 _l[2] usb1 _h[2] f g lrxc ad_l [3] vss ldtc omp0 ldtc omp1 nc8 vss vdd_ core x clkr un_l usbo c_l[0 ] nc31 vss vdd_ usb g h nc0 lrxc lk_l lrxc lk_h vss lrxc ad_h [4] vdd_ core vdd_ core x nc13 usbo c_l[1 ] nc32 vss vdd_ usb h j nc6 vss lrxc ad_h [5] lrxc ad_l [5] lrxc ad_l [4] vdd_ core vdd_ core x vss_ usba usb_ rext vss usb0 _h[2] usb0 _l[2] j k lrxc tl_h nc15 nc17 vss lrxc ad_h [6] vdd_ core vdd_ core x vdd_ usba vss_ usba usb0 _h[1] usb0 _l[1] vss k l lrxc tl_l vss lrxc ad_h [7] lrxc ad_l [7] lrxc ad_l [6] vss vss vss vss vss vss vdd_ usba vss vss usb0 _h[0] usb0 _l[0] l m nc11 ltxc tl_h ltxc tl_l vss ltxc ad_l [7] vss vss vss vss vss vss vdd_ iox vdd_ iox vss vss vss m n nc14 vss ltxc ad_l [6] ltxc ad_h [6] ltxc ad_h [7] vss vss vss vss vss vss smb usd0 rtcx _out intr uder _l rtcx _in s3pl l_lf n p ltxc lk_l nc16 nc18 vss ltxc ad_l [5] vss vss vss vss vss vss smb usc0 gpio 14 ldtr st_l s3pl l_lf _vss pwr ok p r ltxc lk_h vss ltxc ad_l [4] ltxc ad_h [4] ltxc ad_h [5] vss vss vss vss vss vss vdd_ iox vdd_ iox pwr btn_ l vss exts mi_l r t ltxc ad_l [2] ltxc ad_h [3] ltxc ad_l [3] vss ldtc omp2 vss vss vss vss vss vss nc4 dcst op_l rpw ron smb aler t0_l slpb tn_l t u ltxc ad_h [2] vss nc5 nc1 ldtc omp3 vdd_ core vdd_ core x smb usd1 lid pwr on_l acav smb aler t1_l u v ltxc ad_l [0] ltxc ad_h [1] ltxc ad_l [1] vss vss vdd_ core vdd_ core x vdd_ iox vdd_ iox susp end_ l vss smb usc1 v w ltxc ad_h [0] vss vss vdd_ ldt vss vdd_ core vdd_ core x mii_c ol mii_c rs c32k hz ri_l batl ow_l w y vdd_ ldt vdd_ ldt vdd_ ldt pirq c_l pirq a_l vdd_ core vdd_ core x mii_t x_cl k mii_r x_er mii_p hy_r st pme_ l rese t_l y aa pirq b_l pirq d_l ad30 vdd_ io ad31 vss vss vdd_ core vdd_ core vdd_ core vdd_ io vdd_ io vdd_ io vdd_ io vdd_ core x mii_r x_dv vdd_ iox mii_t x_en vss mii_r x_cl k aa ab ad29 ad28 ad27 ad16 fra me_l ad15 ad13 cbe_ l[0] ad4 ad2 req_ l[0] gnt_ l[2] req_ l[5] gnt_ l[6] ldts top_ l accl k stra pl2 ldtr eq_l nc24 nc3 stra pl0 vdd_ iox mii_r xd1 mii_t xd1 mii_r xd0 mii_t xd0 ab ac ad26 vss ad25 vdd_ io irdy _l cbe_ l[1] vdd_ io ad8 ad3 vdd_ io gnt_ l[0] req_ l[3] vdd_ io pnpi rq2 fanc on_0 vdd_ io gpio 30 stra pl3 vdd_ io nc23 vdd_ io vss vdd_ iox mii_t xd3 mii_r xd2 mii_t xd2 ac ad ad24 cbe_ l[3] ad20 ad17 trdy _l perr _l ad11 ad12 ad7 ad0 req_ l[1] gnt_ l[3] gnt_ l[5] pclk pgnt _l fanc on_1 ther mtri p_l gpio 27 gpio 16 stra pl1 nc25 gpio 4 acsd i1 vdd_ iox vss mii_r xd3 ad ae ad23 vss ad19 vss devs el_l serr _l vss ad10 ad6 vss gnt_ l[1] req_ l[4] vss pcist op_l pnpi rq0 vss cpus leep _l agps top_ l vss preq _l gpio 17 vss nc26 vss vdd_ iox mii_ mdc ae af ad22 ad21 ad18 cbe_ l[2] stop _l par ad14 ad9 ad5 ad1 req_ l[2] gnt_ l[4] req_ l[6] usbc lk pnpi rq1 fanr pm cpus top_ l ther m_l acsd o acsy nc nc27 gpio 28 acrs t_l acsd i0 mii_ mdio vss af 1234567891011121314151617181920212223242526 362 pin designations chapter 6 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information table 81. alphabetical listing of signals and corresponding bga designators ball signal ball signal ball signal u25 acav f1 lrxcad_h[3] y6 vdd_core ab16 acclk h5 lrxcad_h[4] f7 vdd_core af23 acrst_l j3 lrxcad_h[5] f8 vdd_core af24 acsdi0 k5 lrxcad_h[6] g21 vdd_corex ad23 acsdi1 l3 lrxcad_h[7] h21 vdd_corex af19 acsdo h2 lrxclk_l j21 vdd_corex af20 acsync h3 lrxclk_h k21 vdd_corex ad10 ad0 l1 lrxctl_l u21 vdd_corex af10 ad1 k1 lrxctl_h v21 vdd_corex ab10 ad2 v1 ltxcad_l[0] w21 vdd_corex ac9 ad3 v3 ltxcad_l[1] y21 vdd_corex ab9 ad4 t1 ltxcad_l[2] aa21 vdd_corex af9 ad5 t3 ltxcad_l[3] d6 vdd_io ae9 ad6 r3 ltxcad_l[4] ac4 vdd_io ad9 ad7 p5 ltxcad_l[5] f17 vdd_io ac8 ad8 n3 ltxcad_l[6] f18 vdd_io af8 ad9 m5 ltxcad_l[7] d20 vdd_io ae8 ad10 w1 ltxcad_h[0] d17 vdd_io ad7 ad11 v2 ltxcad_h[1] f19 vdd_io ad8 ad12 u1 ltxcad_h[2] f20 vdd_io ab7 ad13 t2 ltxcad_h[3] d23 vdd_io af7 ad14 r4 ltxcad_h[4] aa17 vdd_io ab6 ad15 r5 ltxcad_h[5] aa18 vdd_io ab4 ad16 n4 ltxcad_h[6] aa19 vdd_io ad4 ad17 n5 ltxcad_h[7] aa20 vdd_io af3 ad18 p1 ltxclk_l ac21 vdd_io ae3 ad19 r1 ltxclk_h ac16 vdd_io ad3 ad20 m3 ltxctl_l ac19 vdd_io af2 ad21 m2 ltxctl_h ac7 vdd_io af1 ad22 w22 mii_col d8 vdd_io ae1 ad23 w23 mii_crs ac10 vdd_io ad1 ad24 ae26 mii_mdc d11 vdd_io ac3 ad25 af25 mii_mdio ac13 vdd_io ac1 ad26 y24 mii_phy_rst d14 vdd_io ab3 ad27 aa26 mii_rx_clk aa4 vdd_io ab2 ad28 aa22 mii_rx_dv m22 vdd_iox ab1 ad29 y23 mii_rx_er ad24 vdd_iox aa3 ad30 ab25 mii_rxd0 ae25 vdd_iox aa5 ad31 ab23 mii_rxd1 r22 vdd_iox ae18 agpstop_l ac25 mii_rxd2 v22 vdd_iox w26 batlow_l ad26 mii_rxd3 ab22 vdd_iox chapter 6pin designations 363 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information w24 c32khz y22 mii_tx_clk m23 vdd_iox ab8 cbe_l[0] aa24 mii_tx_en r23 vdd_iox ac6 cbe_l[1] ab26 mii_txd0 v23 vdd_iox af4 cbe_l[2] ab24 mii_txd1 aa23 vdd_iox ad2 cbe_l[3] ac26 mii_txd2 ac23 vdd_iox g22 clkrun_l ac24 mii_txd3 y1 vdd_ldt ae17 cpusleep_l h1 nc0 y2 vdd_ldt af17 cpustop_l u4 nc1 y3 vdd_ldt c14 daddrp0 e3 nc2 w4 vdd_ldt e14 daddrp1 ab20 nc3 c1 vdd_ldt a13 daddrp2 t22 nc4 c2 vdd_ldt b7 daddrs0 u3 nc5 c3 vdd_ldt a7 daddrs1 j1 nc6 d4 vdd_ldt c7 daddrs2 f5 nc7 a26 vdd_ref b13 dcs1p_l g5 nc8 a23 vdd_rtc e7 dcs1s_l e6 nc9 g26 vdd_usb c13 dcs3p_l a1 nc10 h26 vdd_usb d7 dcs3s_l m1 nc11 k22 vdd_usba t23 dcstop_l a2 nc12 l22 vdd_usba d15 ddackp_l h22 nc13 f24 vss e8 ddacks_l n1 nc14 d24 vss e16 ddatap0 k2 nc15 e23 vss b16 ddatap1 p2 nc16 l24 vss c17 ddatap2 k3 nc17 m26 vss a17 ddatap3 p3 nc18 m25 vss e18 ddatap4 a3 nc19 g25 vss b18 ddatap5 e5 nc20 e26 vss d19 ddatap6 a5 nc21 j24 vss c19 ddatap7 c6 nc22 c26 vss e19 ddatap8 ac20 nc23 b6 vss a18 ddatap9 ab19 nc24 l23 vss c18 ddatap10 ad21 nc25 h25 vss d18 ddatap11 ae23 nc26 m24 vss e17 ddatap12 af21 nc27 ac22 vss a16 ddatap13 a6 nc28 u2 vss c16 ddatap14 c5 nc29 w2 vss d16 ddatap15 a4 nc30 ac2 vss a9 ddatas0 g24 nc31 ae2 vss e10 ddatas1 h24 nc32 b3 vss b10 ddatas2 c20 osc w3 vss c11 ddatas3 af6 par c4 vss table 81. alphabetical listing of signals and corresponding bga designators (continued) ball signal ball signal ball signal 364 pin designations chapter 6 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information a11 ddatas4 ae14 pcistop_l f4 vss e12 ddatas5 ad14 pclk h4 vss b12 ddatas6 ad6 perr_l b1 vss d13 ddatas7 ad15 pgnt_l k4 vss a12 ddatas8 y5 pirqa_l m4 vss c12 ddatas9 aa1 pirqb_l p4 vss d12 ddatas10 y4 pirqc_l t4 vss e11 ddatas11 aa2 pirqd_l v4 vss a10 ddatas12 y25 pme_l ae4 vss c10 ddatas13 ae15 pnpirq0 v5 vss d10 ddatas14 af15 pnpirq1 w5 vss b9 ddatas15 ac14 pnpirq2 b2 vss a15 ddrqp e21 prdy f6 vss c9 ddrqs ae20 preq_l g6 vss ae5 devsel_l r24 pwrbtn_l aa6 vss c15 diorp_l p26 pwrok ae7 vss d9 diors_l u24 pwron_l aa7 vss b15 diowp_l ab11 req_l[0] b8 vss e9 diows_l ad11 req_l[1] ae10 vss e15 drdyp af11 req_l[2] l11 vss a8 drdys ac12 req_l[3] m11 vss b19 drstp_l ae12 req_l[4] n11 vss e13 drsts_l ab13 req_l[5] e2 vss r26 extsmi_l af13 req_l[6] p11 vss ac15 fancon_0 y26 reset_l r11 vss ad16 fancon_1 w25 ri_l t11 vss af16 fanrpm t24 rpwron b11 vss ab5 frame_l n25 rtcx_in l12 vss ac11 gnt_l[0] n23 rtcx_out m12 vss ae11 gnt_l[1] n26 s3pll_lf n12 vss ab12 gnt_l[2] p25 s3pll_lf_vss p12 vss ad12 gnt_l[3] c23 serirq r12 vss af12 gnt_l[4] ae6 serr_l t12 vss ad13 gnt_l[5] t26 slpbtn_l g2 vss ab14 gnt_l[6] t25 smbalert0_l ae13 vss p23 gpio14 u26 smbalert1_l l13 vss ad19 gpio16 p22 smbusc0 m13 vss ae21 gpio17 v26 smbusc1 n13 vss b26 gpio26 n22 smbusd0 p13 vss ad18 gpio27 u22 smbusd1 r13 vss af22 gpio28 b21 spkr t13 vss table 81. alphabetical listing of signals and corresponding bga designators (continued) ball signal ball signal ball signal chapter 6pin designations 365 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information e20 gpio29 af5 stop_l l14 vss ac17 gpio30 b5 straph0 m14 vss f23 gpio31 d5 straph1 n14 vss ad22 gpio4 e4 straph2 j2 vss c24 gpio8 b4 straph3 p14 vss c21 intirq8_l ab21 strapl0 r14 vss n24 intruder_l ad20 strapl1 t14 vss ac5 irdy_l ab17 strapl2 b14 vss b24 irq1 ac18 strapl3 l15 vss e22 irq12 v24 suspend_l m15 vss a14 irq14 f22 test_l n15 vss c8 irq15 af18 therm_l p15 vss a22 irq6 ad17 thermtrip_l r15 vss a25 ka20g ad5 trdy_l t15 vss c22 kbrc_l j23 usb_rext l2 vss b22 lad0 l26 usb0_l[0] ae16 vss d22 lad1 k25 usb0_l[1] l16 vss a20 lad2 j26 usb0_l[2] m16 vss a21 lad3 l25 usb0_h[0] n16 vss a19 ldrq_l[0] k24 usb0_h[1] p16 vss d21 ldrq_l[1] j25 usb0_h[2] r16 vss g3 ldtcomp0 d25 usb1_l[0] t16 vss g4 ldtcomp1 e24 usb1_l[1] b17 vss t5 ldtcomp2 f25 usb1_l[2] b20 vss u5 ldtcomp3 d26 usb1_h[0] ae19 vss ab18 ldtreq_l e25 usb1_h[1] b23 vss p24 ldtrst_l f26 usb1_h[2] n2 vss ab15 ldtstop_l af14 usbclk f21 vss a24 lframe_l g23 usboc_l[0] ae22 vss u23 lid h23 usboc_l[1] b25 vss d2 lrxcad_l[0] h6 vdd_core ae24 vss e1 lrxcad_l[1] f9 vdd_core c25 vss f2 lrxcad_l[2] f10 vdd_core k26 vss g1 lrxcad_l[3] aa8 vdd_core r25 vss j5 lrxcad_l[4] aa9 vdd_core v25 vss j4 lrxcad_l[5] aa10 vdd_core aa25 vss l5 lrxcad_l[6] j6 vdd_core ad25 vss l4 lrxcad_l[7] k6 vdd_core r2 vss d3 lrxcad_h[0] u6 vdd_core af26 vss d1 lrxcad_h[1] v6 vdd_core j22 vss_usba f3 lrxcad_h[2] w6 vdd_core k23 vss_usba table 81. alphabetical listing of signals and corresponding bga designators (continued) ball signal ball signal ball signal 366 pin designations chapter 6 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information chapter 7 package speci?cation 367 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information chapter 7 p ackage speci?ation 368 package speci?cation chapter 7 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information chapter 7 package speci?cation 369 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information symbol description 1 dimensions and tolerances conform to asme y14.5m 1994. 2 all dimensions are in millimeters. dimension b is measured at the maximum solder ball diameter on a plane parallel to datum c. datum c and the seating plane are de ned by the spherical crowns of the solder balls. the number of peripheral rows and columns. s is measured with respect to datums a and b, and de nes the position of the solder balls nearest the package centerlines. 7 conforms to jep-95, mo-151, issue 9, variation bal-2. the minimum at area top side of the package is used for marking and pickup. the atness speci cation applied to this area. any ejector marks must be outside of this area. optional features. symbol minimum nominal maximum description a 2.20 2.33 2.46 overall thickness a1 0.50 0.60 0.70 ball height a2 0.51 0.56 0.61 body thickness d 35.00 bsc. body size d1 31.75 bsc. ball footprint e 35.00 bsc. body size e1 31.75 bsc. ball footprint m 26 x 26 ball matrix size n 492 total ball count mr 5 number of rows b 0.60 0.75 0.90 ball diameter e 1.27 bsc. ball pitch p 29.9 30.0 30.1 encapsulation area p1 28.0 minimum flat encapsulation area s 0.635 bsc. solder ball placement symbol tolerance description aaa 0.15 coplanarity bbb 0.15 parallelism ccc 0.15 flatness 3 4 5 6 8 9 5 370 package speci?cation chapter 7 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information chapter 8 test 371 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information chapter 8 test 8.1 pin select options the device includes a number of test modes which are entered through pin selection. these modes are entered by asserting the following pins: 8.1.1 nand tree mode the device includes a number of nand trees around the periphery that can be used for continuity testing. the nand trees are connected in the following order: note: all lrxcad inputs to the nand tree are differential. table 82. pin select options mode equation to enable mode high impedance ~test_l & pwrok & ~preq_l & ~serr_l nand tree ~test_l & pwrok & ~preq_l & serr_l table 84. nand tree 1: output gnt_l[0] 1 ldtcomp2 11 lrxcad_h/l[5] 21 ltxcad_h[2] 31 ltxcad_h[7] 2 ldtcomp3 12 lrxcad_h/l[6] 22 ltxcad_l[2] 32 ltxcad_l[7] 3 ldtcomp0 13 lrxcad_h/l[7] 23 ltxcad_h[3] 33 ltxctl_h 4 ldtcomp1 14 lrxctl_h/l 24 ltxcad_l[3] 34 ltxctl_l 5 lrxclk_h/l 15 ltxclk_h 25 ltxcad_h[4] 35 6 lrxcad_h/l[0] 16 ltxclk_l 26 ltxcad_l[4] 36 7 lrxcad_h/l[1] 17 ltxcad_h[0] 27 ltxcad_h[5] 37 8 lrxcad_h/l[2] 18 ltxcad_l[0] 28 ltxcad_l[5] 38 9 lrxcad_h/l[3] 19 ltxcad_h[1] 29 ltxcad_h[6] 39 10 lrxcad_h/l[4] 20 ltxcad_l[1] 30 ltxcad_l[6] 40 372 test chapter 8 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information table 85. nand tree 2: output gnt_l[1] 1 pirqb_l 11 cbe_l[3] 21 ad17 31 cbe_l[0] 41 ad9 2 ad29 12 ad23 22 irdy_l 32 ad11 42 ad7 3 pirqd_l 13 ad31 23 ad15 33 stop_l 43 ad6 4 ad28 14 ad16 24 trdy_l 34 ad8 44 ad0 5 ad30 15 ad25 25 ad18 35 ad4 45 ad2 6 pirqc_l 16 ad20 26 cbe_l[1] 36 par 46 ad5 7 ad26 17 ad22 27 ad13 37 ad14 47 req_l[1] 8 ad24 18 ad21 28 perr_l 38 ad3 48 ad1 9 ad27 19 ad19 29 devsel_l 39 ad12 49 10 pirqa_l 20 frame_l 30 cbe_l[2] 40 ad10 50 table 86. nand tree 3: output nc24 1 req_l[2] 10 usbclk 19 therm_l 28 acclk 37 nc25 2 req_l[0] 11 pnpirq1 20 cpusleep_l 29 nc27 38 gpio4 3 gnt_l[2] 12 req_l[5] 21 acsdo 30 gpio28 39 ldtreq_l 4 req_l[4] 13 pnpirq0 22 fancon_0 31 gpio30 40 nc 5 gnt_l[4] 14 pgnt_l 23 ldtstop_l 32 gpio17 41 6 req_l[6] 15 fanrpm 24 fancon_1 33 gpio16 42 7 gnt_l[5] 16 pnpirq2 25 acsync 34 strapl3 43 8 req_l[3] 17 gnt_l[6] 26 thermtrip_l 35 strapl2 44 9 pcistop_l 18 cpustop_l 27 gpio27 36 strapl1 45 table 87. nand tree 4: output dcstop_l 1 usb1_h[2] 13 intruder_l 25 mii_txd1 37 mii_phy_rst 49 smbalert1_l 2 usb1_l[2] 14 agpstop_l 26 mii_rx_dv 38 c32khz 50 rpwron 3 usb1_h[1] 15 acrst_l 27 mii_rxd2 39 pme_l 51 smbusd0 4 usb1_l[1] 16 nc26 28 mii_txd2 40 reset_l 52 smbalert0_l 5 usb1_h[0] 17 acsdi1 29 mii_tx_clk 41 suspend_l 53 pwrbtn_l 6 usb1_l[0] 18 acsdi0 30 mii_rx_er 42 ri_l 54 slpbtn_l 7 usb0_h[2] 19 mii_mdio 31 mii_txd0 43 batlow_l 55 extsmi_l 8 usb0_l[2] 20 strapl0 32 mii_tx_en 44 lid 56 gpio14 9 usb0_h[1] 21 mii_mdc 33 mii_rxd0 45 smbusd1 57 smbusc0 10 usb0_l[1] 22 mii_rxd3 34 mii_col 46 pwron_l 58 ldtrst_l 11 usb0_h[0] 23 mii_txd3 35 mii_crs 47 smbusc1 59 12 usb0_l[0] 24 mii_rxd1 36 mii_rx_clk 48 acav 60 chapter 8 test 373 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information the following pins are not part of the nand tree: rtcx_in, rtcx_out, s3pll_lf, s3pll_lf_vss, usb_rext, pwrok, pclk, test_l, preq_l, serr_l. each of the above columns show the nand tree, with the last signal used as the output. for example, the ?st column is connected as follows: table 88. nand tree 5: output diowp_l 1 usboc_l[1] 11 irq12 21 ddatap8 31 ddatap10 41 ddatap3 2 usboc_l[0] 12 lad1 22 ddatap4 32 drstp_l 42 daddrp1 3 gpio26 13 kbrc_l 23 lad3 33 ddatap0 43 diorp_l 4 clkrun_l 14 lad0 24 ddatap6 34 ddatap15 44 ddatap1 5 ka20g 15 irq6 25 osc 35 ddatap9 45 ddatap13 6 gpio31 16 prdy 26 ddatap7 36 ddatap2 46 drsts_l 7 gpio8 17 ldrq_l[1] 27 ddatap11 37 ddatap5 47 daddrp0 8 irq1 18 intirq8_l 28 lad2 38 drdyp 48 9 lframe_l 19 gpio29 29 ddatap12 39 ddackp_l 49 10 serirq 20 spkr 30 ldrq_l[0] 40 ddatap14 50 table 89. nand tree 6: output gnt_l[3] 1 ddrqp 11 ddatas6 21 ddatas15 31 dcs3s_l 41 nc19 2 ddatas7 12 ddatas8 22 drdys 32 dcs1s_l 42 nc20 3 irq14 13 ddatas3 23 diors_l 33 nc28 43 straph2 4 dcs3p_l 14 ddatas4 24 ddrqs 34 nc22 44 5 dcs1p_l 15 ddatas12 25 diows_l 35 nc21 45 6 ddatas10 16 ddatas2 26 irq15 36 straph0 46 7 ddatas5 17 ddatas14 27 daddrs1 37 nc29 47 8 ddatas9 18 ddatas1 28 daddrs0 38 nc30 48 9 ddatas11 19 ddatas13 29 daddrs2 39 straph3 49 10 daddrp2 20 ddatas0 30 ddacks_l 40 strah1 50 nand tree mode 1 0 output signal to output signal signal_41 vdd signal_1 signal_2 + - signal_3_p signal_3_n ... ... 374 test chapter 8 AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information 8.1.2 high impedance m ode if this mode is entered all bidirectional and open-drain pins are switched into high-z state. appendix a glossary 375 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information appendix a glossary application processor. in a multiprocessor system, an application processor is any cpu except the boot processor. boot processor. in a multiprocessor system, the boot processor is the processor that initializes the system. fon. system full on state which occurs when the main and aux planes are powered. function. a function is like a separate pci device within a pci peripheral. see ?.7.4.1 con?uration mechanism #1?of the revision 2.1 pci speci?ation for details on how functions are mapped in con?uration address space. ioapic. i/o advanced programmable interrupt controller. this term refers to the industry-standard register de?itions. moff. system mechanical off state which occurs when the aux planes are not powered. mp. multiprocessor. offset. this generally refers to the value that must be added to a base address pointer to address a speci? register. pic. programmable interrupt controller. this term refers to the dual-8259-based system interrupt control as found in the original at isa bus. pit. programmable interval timer. this is a legacy isa-bus device that is incorporated into the logic. it is used to generate interrupts from timers. pos. system power on suspend state. the aux and main planes are powered in this state; the processor and potentially other system components are not functional when in this state. power button override event. this event occurs when pwrbtn_l is held active for at least four seconds. the ic transitions to the soff state, if this event occurs. soff. system soft off state which occurs when the aux planes are powered but the main plane is not powered. str. system suspend to ram state. in this state, only the aux planes are powered in the ic; most of the rest of the system is powered down except resume logic and the system dram. usb. universal serial bus. 376references appendix b AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information appendix b references advanced con?uration and power interface speci?ation revision 1.0. by intel, microsoft, and toshiba. copyright 1996, 1997. advanced con?uration and power interface speci?ation revision 2.0. by compaq, intel, microsoft, phoenix, and toshiba. copyright 2000. hydra asic design speci?ation. revision 1.2, dated 11-sep-96, by compaq. hypertransport i/o link protocol speci?ation, revision 1.02. from the hypertransport technology consortium, www.hypertransport.org. low pin count (lpc) interface speci?ation, revision 1.0. from intel corporation. multiprocessor speci?ation, version 1.4, august 1996. from intel corporation. openhci for usb. release 1.0a, dated 9-mar-97, by compaq, microsoft, and national semiconductor. mobile pc/pci dma arbitration and protocols. revision 2.2, dated 22-apr-96, by intel corporation. pci ide controller speci?ation, revision 1.0. dated 4-mar-94. by the pci special interest group, po box 14070, portland, or, 97214, (800) 433-5177. pci mobile design guide, version 1.1. dated 18-dec-98. by the pci special interest group, po box 14070, portland, or, 97214, (800) 433-5177. pci system architecture, third edition. by tom shanley and don anderson. copyright 1995, by mindshare, inc., isbn: 0-201-40993-3. revision 2.1 pci speci?ation. by the pci special interest group, po box 14070, portland, or, 97214, (800) 433-5177. copyright 1992, 1993, and 1995 by the pci special interest group. serial irq speci?ation version 1.0. vesa (video electronics standards association), 2150 north first street, suite 440, san jose, ca, 95131-2029, phone: (408) 435-0333. system management bus speci?ation revision 1.0. dated 15-feb-95. copyright 1996. written by benchmarq microelectronics inc., duracell inc., energizer power systems, intel corporation, linear technology corporation, maxim integrated products, mitsubishi electric corporation, national semiconductor corporation, toshiba battery co., varta batterie ag. universal serial bus speci?ation revision 1.0. by compaq, dec, ibm, intel, microsoft, nec, and northern telecom. copyright 1995, 1996. appendix c conventions 377 24674 rev. 3.00 april 2003 AMD-8111? hypertransport? i/o hub data sheet amd preliminary information appendix c conventions in this speci?ation, all formulae and number schemes follow verilog numerical conventions. here is a brief summary: y?x ? means that the number that follows it, x, is in hexadecimal format. if there is a number before the ?, y, speci?s the number of bits in x. {} these brackets are used to indicate a group of bits that are concatenated together. | this is the logical or operator. & this is the logical and operator. ~ this is the logical not operator. == this is the logical ?s equal to?operator. != this is the logical ?s not equal to?operator. * multiply. the order in which the operators are applied is: ~ ?st, & second, and | last. 378 conventions appendix c AMD-8111? hypertransport? i/o hub data sheet 24674 rev. 3.00 april 2003 amd preliminary information |
Price & Availability of AMD-8111
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |